/macosx-10.10/libtelnet-13/ |
H A D | auth-proto.h | 101 #ifdef SRA
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H A D | auth.c | 178 #ifdef SRA
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H A D | sra.c | 37 #ifdef SRA 145 printf("Trying SRA secure login:\r\n"); 155 /* server received an IS -- could be SRA KEY, USER, or PASS */ 171 printf("SRA user rejected for bad PKB\r\n"); 220 printf("SRA user accepted\r\n"); 231 printf("SRA user failed\r\n"); 238 printf("Unknown SRA option %d\r\n", data[-1]); 246 /* client received REPLY -- could be SRA KEY, CONTINUE, ACCEPT, or REJECT */ 262 printf("SRA user rejected for bad PKB\r\n"); 304 printf("[ SRA logi [all...] |
/macosx-10.10/llvmCore-3425.0.34/lib/Target/ARM/ |
H A D | ARMSelectionDAGInfo.h | 28 case ISD::SRA: return ARM_AM::asr;
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/macosx-10.10/Heimdal-398.1.2/appl/telnet/libtelnet/ |
H A D | auth-proto.h | 91 #ifdef SRA
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H A D | auth.c | 119 #ifdef SRA
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/macosx-10.10/llvmCore-3425.0.34/include/llvm/CodeGen/ |
H A D | ISDOpcodes.h | 316 SHL, SRA, SRL, ROTL, ROTR, enumerator in enum:llvm::ISD::NodeType 380 /// SIGN_EXTEND_INREG - This operator atomically performs a SHL/SRA pair to
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/macosx-10.10/llvmCore-3425.0.34/lib/Target/MSP430/ |
H A D | MSP430ISelLowering.h | 64 /// SHL, SRA, SRL - Non-constant shifts. 65 SHL, SRA, SRL enumerator in enum:llvm::MSP430ISD::__anon10490
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H A D | MSP430ISelLowering.cpp | 95 setOperationAction(ISD::SRA, MVT::i8, Custom); 98 setOperationAction(ISD::SRA, MVT::i16, Custom); 185 case ISD::SRA: return LowerShifts(Op, DAG); 604 case ISD::SRA: 605 return DAG.getNode(MSP430ISD::SRA, dl, 824 SR = DAG.getNode(ISD::SRA, dl, MVT::i16, SR, One); 984 case MSP430ISD::SRA: return "MSP430ISD::SRA";
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/macosx-10.10/llvmCore-3425.0.34/lib/CodeGen/SelectionDAG/ |
H A D | LegalizeIntegerTypes.cpp | 74 case ISD::SRA: Res = PromoteIntRes_SRA(N); break; 558 return DAG.getNode(ISD::SRA, N->getDebugLoc(), 795 case ISD::SRA: 1161 case ISD::SRA: 1329 assert(N->getOpcode() == ISD::SRA && "Unknown shift!"); 1331 Hi = Lo = DAG.getNode(ISD::SRA, DL, NVT, InH, 1334 Lo = DAG.getNode(ISD::SRA, DL, NVT, InH, 1336 Hi = DAG.getNode(ISD::SRA, DL, NVT, InH, 1340 Hi = DAG.getNode(ISD::SRA, DL, NVT, InH, 1348 Hi = DAG.getNode(ISD::SRA, D [all...] |
H A D | FastISel.cpp | 396 ISDOpcode = ISD::SRA; 974 return SelectBinaryOp(I, ISD::SRA); 1139 if ((Opcode == ISD::SHL || Opcode == ISD::SRA || Opcode == ISD::SRL) &&
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H A D | DAGCombiner.cpp | 877 if (Opc == ISD::SRA) 1119 case ISD::SRA: return visitSRA(N); 1202 case ISD::SRA: 1882 SDValue SGN = DAG.getNode(ISD::SRA, N->getDebugLoc(), VT, N0, 1894 SDValue SRA = DAG.getNode(ISD::SRA, N->getDebugLoc(), VT, ADD, local 1900 return SRA; 1902 AddToWorkList(SRA.getNode()); 1904 DAG.getConstant(0, VT), SRA); 2083 return DAG.getNode(ISD::SRA, 3765 SDValue SRA = DAG.getNode(ISD::SRA, N->getDebugLoc(), LargeVT, local [all...] |
H A D | SelectionDAGBuilder.h | 491 void visitAShr(const User &I) { visitShift(I, ISD::SRA); }
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H A D | SelectionDAGDumper.cpp | 172 case ISD::SRA: return "sra";
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H A D | LegalizeDAG.cpp | 1271 case ISD::SRA: 2777 Tmp1 = DAG.getNode(ISD::SRA, dl, Node->getValueType(0), Tmp1, ShiftCst); 3358 // The high part is obtained by SRA'ing all but one of the bits of low 3361 SDValue HiLHS = DAG.getNode(ISD::SRA, dl, VT, RHS, 3363 SDValue HiRHS = DAG.getNode(ISD::SRA, dl, VT, LHS, 3385 Tmp1 = DAG.getNode(ISD::SRA, dl, VT, BottomHalf, Tmp1); 3532 case ISD::SRA: 3535 // Scalarize vector SRA/SRL/SHL.
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H A D | LegalizeVectorOps.cpp | 18 // expanded. Similarly, suppose we have an ISD::SRA of type v16i8 on PowerPC; 188 case ISD::SRA:
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H A D | SelectionDAG.cpp | 1860 case ISD::SRA: 2140 /// information. For example, immediately after an "SRA X, 2", we know that 2179 case ISD::SRA: 2181 // SRA X, C -> adds C sign bits. 2729 case ISD::SRA: return getConstant(C1.ashr(C2), VT); 2853 case ISD::SRA: 3114 case ISD::SRA: 3172 case ISD::SRA: 6021 case ISD::SRA:
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/macosx-10.10/emacs-93/emacs/lisp/progmodes/ |
H A D | mixal-mode.el | 944 (SRA miscellaneous "shift right A" 6
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/macosx-10.10/llvmCore-3425.0.34/lib/Target/PowerPC/ |
H A D | PPCISelLowering.h | 91 SRL, SRA, SHL, enumerator in enum:llvm::PPCISD::NodeType
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/macosx-10.10/llvmCore-3425.0.34/lib/Target/CellSPU/ |
H A D | SPUISelLowering.cpp | 244 setOperationAction(ISD::SRA, MVT::i8, Custom); 249 setOperationAction(ISD::SRA, MVT::i64, Legal); 2273 case ISD::SRA: { 2576 SDValue lhsSelectMask = DAG.getNode(ISD::SRA, dl, ccResultVT, 2583 SDValue rhsSelectMask = DAG.getNode(ISD::SRA, dl, ccResultVT, 2754 SDValue sraVal = DAG.getNode(ISD::SRA, 2817 case ISD::SRA: {
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H A D | SPUISelDAGToDAG.cpp | 742 if ((Op0.getOpcode() == ISD::SRA || Op0.getOpcode() == ISD::SRL) 781 } else if (Opc == ISD::SRA) {
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/macosx-10.10/OpenLDAP-499.27/OpenLDAP/libraries/liblunicode/ucdata/ |
H A D | MUTTUCData.txt | 225 E90D;DEVANAGARI SRA LIGATURE;Lo;0;L;;;;;N;;;;;
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/macosx-10.10/llvmCore-3425.0.34/lib/TableGen/ |
H A D | Record.cpp | 921 case SRA: 931 case SRA: Result = LHSv >> RHSv; break; 956 case SRA: Result = "!sra"; break;
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/macosx-10.10/llvmCore-3425.0.34/lib/Target/MBlaze/Disassembler/ |
H A D | MBlazeDisassembler.cpp | 125 case 0x01: return MBlaze::SRA;
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/macosx-10.10/llvmCore-3425.0.34/lib/Target/Mips/ |
H A D | MipsISelLowering.cpp | 690 if (ShiftRightOpc != ISD::SRA && ShiftRightOpc != ISD::SRL) 1392 BuildMI(BB, dl, TII->get(Mips::SRA), Dest) 1617 BuildMI(BB, dl, TII->get(Mips::SRA), Dest) 2206 SDValue ShiftRightHi = DAG.getNode(IsSRA ? ISD::SRA : ISD::SRL, DL, MVT::i32, 2210 SDValue Shift31 = DAG.getNode(ISD::SRA, DL, MVT::i32, Hi,
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