Searched refs:SRA (Results 1 - 25 of 35) sorted by relevance

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/macosx-10.10/libtelnet-13/
H A Dauth-proto.h101 #ifdef SRA
H A Dauth.c178 #ifdef SRA
H A Dsra.c37 #ifdef SRA
145 printf("Trying SRA secure login:\r\n");
155 /* server received an IS -- could be SRA KEY, USER, or PASS */
171 printf("SRA user rejected for bad PKB\r\n");
220 printf("SRA user accepted\r\n");
231 printf("SRA user failed\r\n");
238 printf("Unknown SRA option %d\r\n", data[-1]);
246 /* client received REPLY -- could be SRA KEY, CONTINUE, ACCEPT, or REJECT */
262 printf("SRA user rejected for bad PKB\r\n");
304 printf("[ SRA logi
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/macosx-10.10/llvmCore-3425.0.34/lib/Target/ARM/
H A DARMSelectionDAGInfo.h28 case ISD::SRA: return ARM_AM::asr;
/macosx-10.10/Heimdal-398.1.2/appl/telnet/libtelnet/
H A Dauth-proto.h91 #ifdef SRA
H A Dauth.c119 #ifdef SRA
/macosx-10.10/llvmCore-3425.0.34/include/llvm/CodeGen/
H A DISDOpcodes.h316 SHL, SRA, SRL, ROTL, ROTR, enumerator in enum:llvm::ISD::NodeType
380 /// SIGN_EXTEND_INREG - This operator atomically performs a SHL/SRA pair to
/macosx-10.10/llvmCore-3425.0.34/lib/Target/MSP430/
H A DMSP430ISelLowering.h64 /// SHL, SRA, SRL - Non-constant shifts.
65 SHL, SRA, SRL enumerator in enum:llvm::MSP430ISD::__anon10490
H A DMSP430ISelLowering.cpp95 setOperationAction(ISD::SRA, MVT::i8, Custom);
98 setOperationAction(ISD::SRA, MVT::i16, Custom);
185 case ISD::SRA: return LowerShifts(Op, DAG);
604 case ISD::SRA:
605 return DAG.getNode(MSP430ISD::SRA, dl,
824 SR = DAG.getNode(ISD::SRA, dl, MVT::i16, SR, One);
984 case MSP430ISD::SRA: return "MSP430ISD::SRA";
/macosx-10.10/llvmCore-3425.0.34/lib/CodeGen/SelectionDAG/
H A DLegalizeIntegerTypes.cpp74 case ISD::SRA: Res = PromoteIntRes_SRA(N); break;
558 return DAG.getNode(ISD::SRA, N->getDebugLoc(),
795 case ISD::SRA:
1161 case ISD::SRA:
1329 assert(N->getOpcode() == ISD::SRA && "Unknown shift!");
1331 Hi = Lo = DAG.getNode(ISD::SRA, DL, NVT, InH,
1334 Lo = DAG.getNode(ISD::SRA, DL, NVT, InH,
1336 Hi = DAG.getNode(ISD::SRA, DL, NVT, InH,
1340 Hi = DAG.getNode(ISD::SRA, DL, NVT, InH,
1348 Hi = DAG.getNode(ISD::SRA, D
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H A DFastISel.cpp396 ISDOpcode = ISD::SRA;
974 return SelectBinaryOp(I, ISD::SRA);
1139 if ((Opcode == ISD::SHL || Opcode == ISD::SRA || Opcode == ISD::SRL) &&
H A DDAGCombiner.cpp877 if (Opc == ISD::SRA)
1119 case ISD::SRA: return visitSRA(N);
1202 case ISD::SRA:
1882 SDValue SGN = DAG.getNode(ISD::SRA, N->getDebugLoc(), VT, N0,
1894 SDValue SRA = DAG.getNode(ISD::SRA, N->getDebugLoc(), VT, ADD, local
1900 return SRA;
1902 AddToWorkList(SRA.getNode());
1904 DAG.getConstant(0, VT), SRA);
2083 return DAG.getNode(ISD::SRA,
3765 SDValue SRA = DAG.getNode(ISD::SRA, N->getDebugLoc(), LargeVT, local
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H A DSelectionDAGBuilder.h491 void visitAShr(const User &I) { visitShift(I, ISD::SRA); }
H A DSelectionDAGDumper.cpp172 case ISD::SRA: return "sra";
H A DLegalizeDAG.cpp1271 case ISD::SRA:
2777 Tmp1 = DAG.getNode(ISD::SRA, dl, Node->getValueType(0), Tmp1, ShiftCst);
3358 // The high part is obtained by SRA'ing all but one of the bits of low
3361 SDValue HiLHS = DAG.getNode(ISD::SRA, dl, VT, RHS,
3363 SDValue HiRHS = DAG.getNode(ISD::SRA, dl, VT, LHS,
3385 Tmp1 = DAG.getNode(ISD::SRA, dl, VT, BottomHalf, Tmp1);
3532 case ISD::SRA:
3535 // Scalarize vector SRA/SRL/SHL.
H A DLegalizeVectorOps.cpp18 // expanded. Similarly, suppose we have an ISD::SRA of type v16i8 on PowerPC;
188 case ISD::SRA:
H A DSelectionDAG.cpp1860 case ISD::SRA:
2140 /// information. For example, immediately after an "SRA X, 2", we know that
2179 case ISD::SRA:
2181 // SRA X, C -> adds C sign bits.
2729 case ISD::SRA: return getConstant(C1.ashr(C2), VT);
2853 case ISD::SRA:
3114 case ISD::SRA:
3172 case ISD::SRA:
6021 case ISD::SRA:
/macosx-10.10/emacs-93/emacs/lisp/progmodes/
H A Dmixal-mode.el944 (SRA miscellaneous "shift right A" 6
/macosx-10.10/llvmCore-3425.0.34/lib/Target/PowerPC/
H A DPPCISelLowering.h91 SRL, SRA, SHL, enumerator in enum:llvm::PPCISD::NodeType
/macosx-10.10/llvmCore-3425.0.34/lib/Target/CellSPU/
H A DSPUISelLowering.cpp244 setOperationAction(ISD::SRA, MVT::i8, Custom);
249 setOperationAction(ISD::SRA, MVT::i64, Legal);
2273 case ISD::SRA: {
2576 SDValue lhsSelectMask = DAG.getNode(ISD::SRA, dl, ccResultVT,
2583 SDValue rhsSelectMask = DAG.getNode(ISD::SRA, dl, ccResultVT,
2754 SDValue sraVal = DAG.getNode(ISD::SRA,
2817 case ISD::SRA: {
H A DSPUISelDAGToDAG.cpp742 if ((Op0.getOpcode() == ISD::SRA || Op0.getOpcode() == ISD::SRL)
781 } else if (Opc == ISD::SRA) {
/macosx-10.10/OpenLDAP-499.27/OpenLDAP/libraries/liblunicode/ucdata/
H A DMUTTUCData.txt225 E90D;DEVANAGARI SRA LIGATURE;Lo;0;L;;;;;N;;;;;
/macosx-10.10/llvmCore-3425.0.34/lib/TableGen/
H A DRecord.cpp921 case SRA:
931 case SRA: Result = LHSv >> RHSv; break;
956 case SRA: Result = "!sra"; break;
/macosx-10.10/llvmCore-3425.0.34/lib/Target/MBlaze/Disassembler/
H A DMBlazeDisassembler.cpp125 case 0x01: return MBlaze::SRA;
/macosx-10.10/llvmCore-3425.0.34/lib/Target/Mips/
H A DMipsISelLowering.cpp690 if (ShiftRightOpc != ISD::SRA && ShiftRightOpc != ISD::SRL)
1392 BuildMI(BB, dl, TII->get(Mips::SRA), Dest)
1617 BuildMI(BB, dl, TII->get(Mips::SRA), Dest)
2206 SDValue ShiftRightHi = DAG.getNode(IsSRA ? ISD::SRA : ISD::SRL, DL, MVT::i32,
2210 SDValue Shift31 = DAG.getNode(ISD::SRA, DL, MVT::i32, Hi,

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