Lines Matching refs:SRA
74 case ISD::SRA: Res = PromoteIntRes_SRA(N); break;
558 return DAG.getNode(ISD::SRA, N->getDebugLoc(),
795 case ISD::SRA:
1161 case ISD::SRA:
1329 assert(N->getOpcode() == ISD::SRA && "Unknown shift!");
1331 Hi = Lo = DAG.getNode(ISD::SRA, DL, NVT, InH,
1334 Lo = DAG.getNode(ISD::SRA, DL, NVT, InH,
1336 Hi = DAG.getNode(ISD::SRA, DL, NVT, InH,
1340 Hi = DAG.getNode(ISD::SRA, DL, NVT, InH,
1348 Hi = DAG.getNode(ISD::SRA, DL, NVT, InH, DAG.getConstant(Amt, ShTy));
1396 case ISD::SRA:
1397 Hi = DAG.getNode(ISD::SRA, dl, NVT, InH, // Sign extend high part.
1399 Lo = DAG.getNode(ISD::SRA, dl, NVT, InH, Amt); // Lo part from Hi part.
1418 case ISD::SRA: Op1 = ISD::SRL; Op2 = ISD::SHL; break;
1499 case ISD::SRA:
1501 HiS = DAG.getNode(ISD::SRA, dl, NVT, InH, Amt);
1509 HiL = DAG.getNode(ISD::SRA, dl, NVT, InH, // Sign of Hi part.
1511 LoL = DAG.getNode(ISD::SRA, dl, NVT, InH, AmtExcess); // Lo from Hi part.
1672 Hi = DAG.getNode(ISD::SRA, dl, NVT, Lo,
1815 // The high part is obtained by SRA'ing all but one of the bits of the
1818 Hi = DAG.getNode(ISD::SRA, dl, NVT, Lo,
1886 Hi = DAG.getNode(ExtType == ISD::SEXTLOAD ? ISD::SRA : ISD::SRL, dl,
2082 assert(N->getOpcode() == ISD::SRA && "Unknown shift!");
2127 assert(N->getOpcode() == ISD::SRA && "Unknown shift!");
2157 // The high part is obtained by SRA'ing all but one of the bits of low part.
2159 Hi = DAG.getNode(ISD::SRA, dl, NVT, Lo,
2193 Hi = DAG.getNode(ISD::SRA, dl, Hi.getValueType(), Lo,
2467 case ISD::SRA: