Searched refs:OpNum (Results 1 - 25 of 25) sorted by relevance

/macosx-10.10/llvmCore-3425.0.34/lib/Target/ARM/InstPrinter/
H A DARMInstPrinter.h39 void printSORegRegOperand(const MCInst *MI, unsigned OpNum, raw_ostream &O);
40 void printSORegImmOperand(const MCInst *MI, unsigned OpNum, raw_ostream &O);
42 void printAddrModeTBB(const MCInst *MI, unsigned OpNum, raw_ostream &O);
43 void printAddrModeTBH(const MCInst *MI, unsigned OpNum, raw_ostream &O);
44 void printAddrMode2Operand(const MCInst *MI, unsigned OpNum, raw_ostream &O);
45 void printAM2PostIndexOp(const MCInst *MI, unsigned OpNum, raw_ostream &O);
46 void printAM2PreOrOffsetIndexOp(const MCInst *MI, unsigned OpNum,
48 void printAddrMode2OffsetOperand(const MCInst *MI, unsigned OpNum,
51 void printAddrMode3Operand(const MCInst *MI, unsigned OpNum, raw_ostream &O);
52 void printAddrMode3OffsetOperand(const MCInst *MI, unsigned OpNum,
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H A DARMInstPrinter.cpp263 void ARMInstPrinter::printThumbLdrLabelOperand(const MCInst *MI, unsigned OpNum, argument
265 const MCOperand &MO1 = MI->getOperand(OpNum);
279 void ARMInstPrinter::printSORegRegOperand(const MCInst *MI, unsigned OpNum, argument
281 const MCOperand &MO1 = MI->getOperand(OpNum);
282 const MCOperand &MO2 = MI->getOperand(OpNum+1);
283 const MCOperand &MO3 = MI->getOperand(OpNum+2);
297 void ARMInstPrinter::printSORegImmOperand(const MCInst *MI, unsigned OpNum, argument
299 const MCOperand &MO1 = MI->getOperand(OpNum);
300 const MCOperand &MO2 = MI->getOperand(OpNum+1);
376 unsigned OpNum,
375 printAddrMode2OffsetOperand(const MCInst *MI, unsigned OpNum, raw_ostream &O) argument
463 printAddrMode3OffsetOperand(const MCInst *MI, unsigned OpNum, raw_ostream &O) argument
481 printPostIdxImm8Operand(const MCInst *MI, unsigned OpNum, raw_ostream &O) argument
489 printPostIdxRegOperand(const MCInst *MI, unsigned OpNum, raw_ostream &O) argument
497 printPostIdxImm8s4Operand(const MCInst *MI, unsigned OpNum, raw_ostream &O) argument
506 printLdStmModeOperand(const MCInst *MI, unsigned OpNum, raw_ostream &O) argument
513 printAddrMode5Operand(const MCInst *MI, unsigned OpNum, raw_ostream &O) argument
535 printAddrMode6Operand(const MCInst *MI, unsigned OpNum, raw_ostream &O) argument
548 printAddrMode7Operand(const MCInst *MI, unsigned OpNum, raw_ostream &O) argument
554 printAddrMode6OffsetOperand(const MCInst *MI, unsigned OpNum, raw_ostream &O) argument
564 printBitfieldInvMaskImmOperand(const MCInst *MI, unsigned OpNum, raw_ostream &O) argument
575 printMemBOption(const MCInst *MI, unsigned OpNum, raw_ostream &O) argument
581 printShiftImmOperand(const MCInst *MI, unsigned OpNum, raw_ostream &O) argument
592 printPKHLSLShiftImm(const MCInst *MI, unsigned OpNum, raw_ostream &O) argument
601 printPKHASRShiftImm(const MCInst *MI, unsigned OpNum, raw_ostream &O) argument
611 printRegisterList(const MCInst *MI, unsigned OpNum, raw_ostream &O) argument
621 printSetendOperand(const MCInst *MI, unsigned OpNum, raw_ostream &O) argument
630 printCPSIMod(const MCInst *MI, unsigned OpNum, raw_ostream &O) argument
636 printCPSIFlag(const MCInst *MI, unsigned OpNum, raw_ostream &O) argument
648 printMSRMaskOperand(const MCInst *MI, unsigned OpNum, raw_ostream &O) argument
728 printPredicateOperand(const MCInst *MI, unsigned OpNum, raw_ostream &O) argument
738 printMandatoryPredicateOperand(const MCInst *MI, unsigned OpNum, raw_ostream &O) argument
745 printSBitModifierOperand(const MCInst *MI, unsigned OpNum, raw_ostream &O) argument
754 printNoHashImmediate(const MCInst *MI, unsigned OpNum, raw_ostream &O) argument
759 printPImmediate(const MCInst *MI, unsigned OpNum, raw_ostream &O) argument
764 printCImmediate(const MCInst *MI, unsigned OpNum, raw_ostream &O) argument
769 printCoprocOptionImm(const MCInst *MI, unsigned OpNum, raw_ostream &O) argument
774 printPCLabel(const MCInst *MI, unsigned OpNum, raw_ostream &O) argument
779 printAdrLabelOperand(const MCInst *MI, unsigned OpNum, raw_ostream &O) argument
798 printThumbS4ImmOperand(const MCInst *MI, unsigned OpNum, raw_ostream &O) argument
803 printThumbSRImm(const MCInst *MI, unsigned OpNum, raw_ostream &O) argument
809 printThumbITMask(const MCInst *MI, unsigned OpNum, raw_ostream &O) argument
887 printT2SOOperand(const MCInst *MI, unsigned OpNum, raw_ostream &O) argument
901 printAddrModeImm12Operand(const MCInst *MI, unsigned OpNum, raw_ostream &O) argument
[all...]
/macosx-10.10/llvmCore-3425.0.34/lib/Target/
H A DTargetInstrInfo.cpp34 TargetInstrInfo::getRegClass(const MCInstrDesc &MCID, unsigned OpNum, argument
37 if (OpNum >= MCID.getNumOperands())
40 short RegClass = MCID.OpInfo[OpNum].RegClass;
41 if (MCID.OpInfo[OpNum].isLookupPtrRegClass())
/macosx-10.10/llvmCore-3425.0.34/lib/Target/MSP430/
H A DMSP430AsmPrinter.cpp49 void printOperand(const MachineInstr *MI, int OpNum,
51 void printSrcMemOperand(const MachineInstr *MI, int OpNum,
64 void MSP430AsmPrinter::printOperand(const MachineInstr *MI, int OpNum, argument
66 const MachineOperand &MO = MI->getOperand(OpNum);
111 void MSP430AsmPrinter::printSrcMemOperand(const MachineInstr *MI, int OpNum, argument
113 const MachineOperand &Base = MI->getOperand(OpNum);
114 const MachineOperand &Disp = MI->getOperand(OpNum+1);
121 printOperand(MI, OpNum+1, O, "nohash");
126 printOperand(MI, OpNum, O);
/macosx-10.10/llvmCore-3425.0.34/lib/Target/ARM/
H A DARMAsmPrinter.h60 void printOperand(const MachineInstr *MI, int OpNum, raw_ostream &O,
63 virtual bool PrintAsmOperand(const MachineInstr *MI, unsigned OpNum,
66 virtual bool PrintAsmMemoryOperand(const MachineInstr *MI, unsigned OpNum,
H A DARMAsmPrinter.cpp331 void ARMAsmPrinter::printOperand(const MachineInstr *MI, int OpNum, argument
333 const MachineOperand &MO = MI->getOperand(OpNum);
418 bool ARMAsmPrinter::PrintAsmOperand(const MachineInstr *MI, unsigned OpNum, argument
428 return AsmPrinter::PrintAsmOperand(MI, OpNum, AsmVariant, ExtraCode, O);
430 if (MI->getOperand(OpNum).isReg()) {
432 << ARMInstPrinter::getRegisterName(MI->getOperand(OpNum).getReg())
438 if (!MI->getOperand(OpNum).isImm())
440 O << MI->getOperand(OpNum).getImm();
444 printOperand(MI, OpNum, O);
447 if (MI->getOperand(OpNum)
558 PrintAsmMemoryOperand(const MachineInstr *MI, unsigned OpNum, unsigned AsmVariant, const char *ExtraCode, raw_ostream &O) argument
969 int OpNum = 1; local
1020 int OpNum = (Opcode == ARM::t2BR_JT) ? 2 : 1; local
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H A DThumb2SizeReduction.cpp338 unsigned OpNum = 3; // First 'rest' of operands. local
376 OpNum = 4;
397 OpNum = 0;
406 OpNum = 2;
414 OpNum = 0;
421 OpNum = 2;
471 for (unsigned e = MI->getNumOperands(); OpNum != e; ++OpNum)
472 MIB.addOperand(MI->getOperand(OpNum));
H A DARMLoadStoreOptimizer.cpp783 for (unsigned OpNum = 3, e = MI->getNumOperands(); OpNum != e; ++OpNum)
784 MIB.addOperand(MI->getOperand(OpNum));
H A DARMBaseInstrInfo.cpp4003 unsigned OpNum,
4011 const MachineOperand &MO = MI->getOperand(OpNum);
4066 unsigned OpNum,
4068 assert(MI && OpNum < MI->getDesc().getNumDefs() && "OpNum is not a def");
4071 const MachineOperand &MO = MI->getOperand(OpNum);
4002 getPartialRegUpdateClearance(const MachineInstr *MI, unsigned OpNum, const TargetRegisterInfo *TRI) const argument
4065 breakPartialRegDependency(MachineBasicBlock::iterator MI, unsigned OpNum, const TargetRegisterInfo *TRI) const argument
H A DARMISelLowering.cpp4515 unsigned OpNum = (PFEntry >> 26) & 0x0F; local
4537 if (OpNum == OP_COPY) {
4548 switch (OpNum) {
4566 OpLHS, DAG.getConstant(OpNum-OP_VDUP0, MVT::i32));
4572 DAG.getConstant(OpNum-OP_VEXT1+1, MVT::i32));
4576 OpLHS, OpRHS).getValue(OpNum-OP_VUZPL);
4580 OpLHS, OpRHS).getValue(OpNum-OP_VZIPL);
4584 OpLHS, OpRHS).getValue(OpNum-OP_VTRNL);
/macosx-10.10/llvmCore-3425.0.34/include/llvm/MC/MCParser/
H A DMCParsedAsmOperand.h37 void setMCOperandNum (unsigned OpNum) { MCOperandNum = OpNum; } argument
/macosx-10.10/llvmCore-3425.0.34/lib/Target/Mips/
H A DMipsAsmPrinter.cpp323 bool MipsAsmPrinter::PrintAsmOperand(const MachineInstr *MI, unsigned OpNum, argument
330 const MachineOperand &MO = MI->getOperand(OpNum);
334 return AsmPrinter::PrintAsmOperand(MI,OpNum,AsmVariant,ExtraCode,O);
370 if (OpNum == 0)
372 const MachineOperand &FlagsOP = MI->getOperand(OpNum - 1);
388 unsigned RegOp = OpNum;
394 RegOp = (Subtarget->isLittle()) ? OpNum + 1 : OpNum;
397 RegOp = (Subtarget->isLittle()) ? OpNum : OpNum
419 PrintAsmMemoryOperand(const MachineInstr *MI, unsigned OpNum, unsigned AsmVariant, const char *ExtraCode, raw_ostream &O) argument
[all...]
H A DMipsAsmPrinter.h73 bool PrintAsmMemoryOperand(const MachineInstr *MI, unsigned OpNum,
/macosx-10.10/llvmCore-3425.0.34/lib/Bitcode/Reader/
H A DBitcodeReader.cpp2016 unsigned OpNum = 0; local
2018 if (getValueTypePair(Record, OpNum, NextValueNo, LHS) ||
2019 getValue(Record, OpNum, LHS->getType(), RHS) ||
2020 OpNum+1 > Record.size())
2023 int Opc = GetDecodedBinaryOpcode(Record[OpNum++], LHS->getType());
2027 if (OpNum < Record.size()) {
2032 if (Record[OpNum] & (1 << bitc::OBO_NO_SIGNED_WRAP))
2034 if (Record[OpNum] & (1 << bitc::OBO_NO_UNSIGNED_WRAP))
2040 if (Record[OpNum] & (1 << bitc::PEO_EXACT))
2047 unsigned OpNum local
2063 unsigned OpNum = 0; local
2085 unsigned OpNum = 0; local
2106 unsigned OpNum = 0; local
2131 unsigned OpNum = 0; local
2146 unsigned OpNum = 0; local
2171 unsigned OpNum = 0; local
2182 unsigned OpNum = 0; local
2195 unsigned OpNum = 0; local
2215 unsigned OpNum = 0; local
2239 unsigned OpNum = 0; local
2384 unsigned OpNum = 4; local
2509 unsigned OpNum = 0; local
2521 unsigned OpNum = 0; local
2542 unsigned OpNum = 0; local
2556 unsigned OpNum = 0; local
2579 unsigned OpNum = 0; local
2599 unsigned OpNum = 0; local
2639 unsigned OpNum = 2; local
[all...]
/macosx-10.10/llvmCore-3425.0.34/include/llvm/MC/
H A DMCInstrDesc.h149 int getOperandConstraint(unsigned OpNum, argument
151 if (OpNum < NumOperands &&
152 (OpInfo[OpNum].Constraints & (1 << Constraint))) {
154 return (int)(OpInfo[OpNum].Constraints >> Pos) & 0xf;
/macosx-10.10/llvmCore-3425.0.34/utils/PerfectShuffle/
H A DPerfectShuffle.cpp106 unsigned short OpNum; member in struct:Operator
112 : ShuffleMask(shufflemask), OpNum(opnum), Name(name), Cost(cost) {
394 unsigned OpNum = ShufTab[i].Op ? ShufTab[i].Op->OpNum : 0;
395 assert(OpNum < 16 && "Too few bits to encode operation!");
402 unsigned Val = (CostSat << 30) | (OpNum << 26) | (LHS << 13) | RHS;
/macosx-10.10/llvmCore-3425.0.34/lib/Target/X86/
H A DX86InstrInfo.h360 unsigned getPartialRegUpdateClearance(const MachineInstr *MI, unsigned OpNum,
362 void breakPartialRegDependency(MachineBasicBlock::iterator MI, unsigned OpNum,
367 unsigned OpNum,
H A DX86CodeEmitter.cpp760 unsigned OpNum) {
761 unsigned SrcReg = MI.getOperand(OpNum).getReg();
762 unsigned SrcRegNum = X86_MC::getX86RegNum(MI.getOperand(OpNum).getReg());
H A DX86InstrInfo.cpp3769 getPartialRegUpdateClearance(const MachineInstr *MI, unsigned OpNum, argument
3771 if (OpNum != 0 || !hasPartialRegUpdate(MI->getOpcode()))
3792 breakPartialRegDependency(MachineBasicBlock::iterator MI, unsigned OpNum, argument
3794 unsigned Reg = MI->getOperand(OpNum).getReg();
4018 unsigned OpNum = Ops[0]; local
4028 if (isTwoAddr && NumOps >= 2 && OpNum < 2) {
4030 } else if (OpNum == 0) { // If operand 0
4039 } else if (OpNum == 1) {
4041 } else if (OpNum == 2) {
4043 } else if (OpNum
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H A DX86ISelLowering.cpp4668 /// starting from its index OpIdx. Also tell OpNum which source vector operand.
4672 unsigned NumElems, unsigned &OpNum) {
4692 OpNum = SeenV1 ? 0 : 1;
4670 isShuffleMaskConsecutive(ShuffleVectorSDNode *SVOp, unsigned MaskI, unsigned MaskE, unsigned OpIdx, unsigned NumElems, unsigned &OpNum) argument
/macosx-10.10/llvmCore-3425.0.34/lib/Target/ARM/MCTargetDesc/
H A DARMMCCodeEmitter.cpp264 unsigned getT2AddrModeSORegOpValue(const MCInst &MI, unsigned OpNum,
266 unsigned getT2AddrModeImm8OpValue(const MCInst &MI, unsigned OpNum,
268 unsigned getT2AddrModeImm8OffsetOpValue(const MCInst &MI, unsigned OpNum,
270 unsigned getT2AddrModeImm12OffsetOpValue(const MCInst &MI, unsigned OpNum,
1230 getT2AddrModeSORegOpValue(const MCInst &MI, unsigned OpNum,
1232 const MCOperand &MO1 = MI.getOperand(OpNum);
1233 const MCOperand &MO2 = MI.getOperand(OpNum+1);
1234 const MCOperand &MO3 = MI.getOperand(OpNum+2);
1248 getT2AddrModeImm8OpValue(const MCInst &MI, unsigned OpNum,
1250 const MCOperand &MO1 = MI.getOperand(OpNum);
[all...]
/macosx-10.10/llvmCore-3425.0.34/lib/CodeGen/
H A DRegAllocFast.cpp74 unsigned short LastOpNum; // OpNum on LastUse.
172 LiveRegMap::iterator defineVirtReg(MachineInstr *MI, unsigned OpNum,
174 LiveRegMap::iterator reloadVirtReg(MachineInstr *MI, unsigned OpNum,
177 bool setPhysReg(MachineInstr *MI, unsigned OpNum, unsigned PhysReg);
572 RAFast::defineVirtReg(MachineInstr *MI, unsigned OpNum, argument
597 LRI->LastOpNum = OpNum;
605 RAFast::reloadVirtReg(MachineInstr *MI, unsigned OpNum, argument
612 MachineOperand &MO = MI->getOperand(OpNum);
648 LRI->LastOpNum = OpNum;
653 // setPhysReg - Change operand OpNum i
656 setPhysReg(MachineInstr *MI, unsigned OpNum, unsigned PhysReg) argument
[all...]
/macosx-10.10/llvmCore-3425.0.34/include/llvm/Target/
H A DTargetInstrInfo.h59 /// class constraint for OpNum, or NULL.
61 unsigned OpNum,
904 /// instructions. Other defs of MI's operand OpNum are avoided in the last N
922 getPartialRegUpdateClearance(const MachineInstr *MI, unsigned OpNum, argument
929 /// before MI to eliminate an unwanted dependency on OpNum.
946 breakPartialRegDependency(MachineBasicBlock::iterator MI, unsigned OpNum, argument
/macosx-10.10/llvmCore-3425.0.34/lib/Target/X86/MCTargetDesc/
H A DX86MCCodeEmitter.cpp68 unsigned OpNum) {
69 unsigned SrcReg = MI.getOperand(OpNum).getReg();
70 unsigned SrcRegNum = GetX86RegNum(MI.getOperand(OpNum));
67 getVEXRegisterEncoding(const MCInst &MI, unsigned OpNum) argument
/macosx-10.10/llvmCore-3425.0.34/lib/Target/PowerPC/
H A DPPCISelLowering.cpp4347 unsigned OpNum = (PFEntry >> 26) & 0x0F; local
4364 if (OpNum == OP_COPY) {
4375 switch (OpNum) {

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