Searched refs:MIB (Results 1 - 25 of 39) sorted by relevance

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/macosx-10.10/llvmCore-3425.0.34/lib/Target/CellSPU/
H A DSPUInstrBuilder.h33 addFrameReference(const MachineInstrBuilder &MIB, int FI, int Offset = 0, argument
36 return MIB.addImm(Offset).addFrameIndex(FI);
38 return MIB.addFrameIndex(FI).addImm(Offset);
H A DSPUInstrInfo.cpp356 MachineInstrBuilder MIB; local
364 MIB = BuildMI(&MBB, DL, get(SPU::HBR_LABEL)).addSym(branchLabel);
370 MIB = BuildMI(&MBB, DL, get(SPU::BR));
371 MIB.addMBB(TBB);
374 DEBUG((*MIB).dump());
378 MIB = BuildMI( MBB, findHBRPosition(MBB), DL, get(SPU::HBRA));
379 MIB.addSym(branchLabel);
380 MIB.addMBB(TBB);
384 MIB = BuildMI(&MBB, DL, get(Cond[0].getImm()));
385 MIB
[all...]
/macosx-10.10/llvmCore-3425.0.34/lib/Target/PowerPC/
H A DPPCInstrBuilder.h33 addFrameReference(const MachineInstrBuilder &MIB, int FI, int Offset = 0, argument
36 return MIB.addImm(Offset).addFrameIndex(FI);
38 return MIB.addFrameIndex(FI).addImm(Offset);
/macosx-10.10/llvmCore-3425.0.34/lib/Target/X86/
H A DX86InstrBuilder.h90 addDirectMem(const MachineInstrBuilder &MIB, unsigned Reg) { argument
93 return MIB.addReg(Reg).addImm(1).addReg(0).addImm(0).addReg(0);
98 addOffset(const MachineInstrBuilder &MIB, int Offset) { argument
99 return MIB.addImm(1).addReg(0).addImm(Offset).addReg(0);
107 addRegOffset(const MachineInstrBuilder &MIB, argument
109 return addOffset(MIB.addReg(Reg, getKillRegState(isKill)), Offset);
114 static inline const MachineInstrBuilder &addRegReg(const MachineInstrBuilder &MIB, argument
117 return MIB.addReg(Reg1, getKillRegState(isKill1)).addImm(1)
122 addFullAddress(const MachineInstrBuilder &MIB, argument
127 MIB
148 addFrameReference(const MachineInstrBuilder &MIB, int FI, int Offset = 0) argument
174 addConstantPoolReference(const MachineInstrBuilder &MIB, unsigned CPI, unsigned GlobalBaseReg, unsigned char OpFlags) argument
[all...]
/macosx-10.10/llvmCore-3425.0.34/lib/Target/ARM/
H A DARMExpandPseudoInsts.cpp383 MachineInstrBuilder MIB = BuildMI(MBB, MBBI, MI.getDebugLoc(), local
391 MIB.addReg(D0, RegState::Define | getDeadRegState(DstIsDead));
393 MIB.addReg(D1, RegState::Define | getDeadRegState(DstIsDead));
395 MIB.addReg(D2, RegState::Define | getDeadRegState(DstIsDead));
397 MIB.addReg(D3, RegState::Define | getDeadRegState(DstIsDead));
400 MIB.addOperand(MI.getOperand(OpIdx++));
403 MIB.addOperand(MI.getOperand(OpIdx++));
404 MIB.addOperand(MI.getOperand(OpIdx++));
407 MIB.addOperand(MI.getOperand(OpIdx++));
417 MIB
448 MachineInstrBuilder MIB = BuildMI(MBB, MBBI, MI.getDebugLoc(), local
500 MachineInstrBuilder MIB = BuildMI(MBB, MBBI, MI.getDebugLoc(), local
584 MachineInstrBuilder MIB = BuildMI(MBB, MBBI, MI.getDebugLoc(), TII->get(Opc)); local
841 MachineInstrBuilder MIB = local
853 MachineInstrBuilder MIB = local
945 MachineInstrBuilder MIB = local
976 MachineInstrBuilder MIB = local
1008 MachineInstrBuilder MIB = local
1236 MachineInstrBuilder MIB = local
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H A DThumb1FrameLowering.cpp280 MachineInstrBuilder MIB = local
283 AddDefaultPred(MIB);
284 MIB->copyImplicitOps(&*MBBI);
304 MachineInstrBuilder MIB = BuildMI(MBB, MI, DL, TII.get(ARM::tPUSH)); local
305 AddDefaultPred(MIB);
323 MIB.addReg(Reg, getKillRegState(isKill));
325 MIB.setMIFlags(MachineInstr::FrameSetup);
343 MachineInstrBuilder MIB = BuildMI(MF, DL, TII.get(ARM::tPOP)); local
344 AddDefaultPred(MIB);
354 (*MIB)
[all...]
H A DThumb1RegisterInfo.cpp130 MachineInstrBuilder MIB = local
133 MIB = AddDefaultT1CC(MIB);
135 MIB.addReg(BaseReg).addReg(LdReg, RegState::Kill);
137 MIB.addReg(LdReg).addReg(BaseReg, RegState::Kill);
138 AddDefaultPred(MIB);
242 const MachineInstrBuilder MIB =
245 AddDefaultPred(MIB.addReg(BaseReg, RegState::Kill).addImm(ThisVal));
261 MachineInstrBuilder MIB = BuildMI(MBB, MBBI, dl, TII.get(Opc), DestReg); local
263 MIB
269 MachineInstrBuilder MIB = BuildMI(MBB, MBBI, dl, TII.get(Opc), DestReg); local
[all...]
H A DThumb2SizeReduction.cpp456 MachineInstrBuilder MIB = BuildMI(MBB, MI, dl, TII->get(Opc)); local
458 MIB.addOperand(MI->getOperand(0));
459 MIB.addOperand(MI->getOperand(1));
462 MIB.addImm(OffsetImm / Scale);
467 MIB.addReg(OffsetReg, getKillRegState(OffsetKill));
472 MIB.addOperand(MI->getOperand(OpNum));
475 MIB->setMemRefs(MI->memoperands_begin(), MI->memoperands_end());
478 MIB.setMIFlags(MI->getFlags());
480 DEBUG(errs() << "Converted 32-bit: " << *MI << " to 16-bit: " << *MIB); local
517 MachineInstrBuilder MIB
527 DEBUG(errs() << "Converted 32-bit: " << *MI << " to 16-bit: " <<*MIB); local
674 MachineInstrBuilder MIB = BuildMI(MBB, MI, dl, NewMCID); local
696 DEBUG(errs() << "Converted 32-bit: " << *MI << " to 16-bit: " << *MIB); local
765 MachineInstrBuilder MIB = BuildMI(MBB, MI, dl, NewMCID); local
803 DEBUG(errs() << "Converted 32-bit: " << *MI << " to 16-bit: " << *MIB); local
[all...]
H A DARMBaseInstrInfo.cpp680 MachineInstrBuilder MIB = BuildMI(MBB, I, DL, get(Opc), DestReg); local
681 MIB.addReg(SrcReg, getKillRegState(KillSrc));
683 MIB.addReg(SrcReg, getKillRegState(KillSrc));
684 AddDefaultPred(MIB);
748 MachineInstrBuilder &AddDReg(MachineInstrBuilder &MIB, argument
752 return MIB.addReg(Reg, State);
755 return MIB.addReg(TRI->getSubReg(Reg, SubIdx), State);
756 return MIB.addReg(Reg, State, SubIdx);
823 MachineInstrBuilder MIB = local
827 MIB
844 MachineInstrBuilder MIB = local
858 MachineInstrBuilder MIB = local
990 MachineInstrBuilder MIB = local
1010 MachineInstrBuilder MIB = local
1026 MachineInstrBuilder MIB = local
1174 MachineInstrBuilder MIB = BuildMI(MF, DL, get(ARM::DBG_VALUE)) local
1242 MachineInstrBuilder MIB = BuildMI(MBB, I, Orig->getDebugLoc(), get(Opcode), local
[all...]
H A DARMBaseInstrInfo.h320 const MachineInstrBuilder &AddDefaultPred(const MachineInstrBuilder &MIB) { argument
321 return MIB.addImm((int64_t)ARMCC::AL).addReg(0);
325 const MachineInstrBuilder &AddDefaultCC(const MachineInstrBuilder &MIB) { argument
326 return MIB.addReg(0);
330 const MachineInstrBuilder &AddDefaultT1CC(const MachineInstrBuilder &MIB, argument
332 return MIB.addReg(ARM::CPSR, getDefRegState(true) | getDeadRegState(isDead));
336 const MachineInstrBuilder &AddNoT1CC(const MachineInstrBuilder &MIB) { argument
337 return MIB.addReg(0);
H A DARMInstrInfo.cpp125 MachineInstrBuilder MIB = BuildMI(FirstMBB, MBBI, DL, local
129 MIB.addImm(0);
130 AddDefaultPred(MIB);
H A DARMFastISel.cpp222 const MachineInstrBuilder &AddOptionalDefs(const MachineInstrBuilder &MIB);
224 const MachineInstrBuilder &MIB,
270 ARMFastISel::AddOptionalDefs(const MachineInstrBuilder &MIB) { argument
271 MachineInstr *MI = &*MIB;
277 AddDefaultPred(MIB);
284 AddDefaultT1CC(MIB);
286 AddDefaultCC(MIB);
288 return MIB;
665 MachineInstrBuilder MIB; local
668 MIB
685 MachineInstrBuilder MIB = BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, local
696 MachineInstrBuilder MIB; local
951 AddLoadStoreOperands(EVT VT, Address &Addr, const MachineInstrBuilder &MIB, unsigned Flags, bool useAM3) argument
1087 MachineInstrBuilder MIB = BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, local
1207 MachineInstrBuilder MIB = BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, local
1495 MachineInstrBuilder MIB; local
2244 MachineInstrBuilder MIB = BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, local
2382 MachineInstrBuilder MIB = BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, local
2604 MachineInstrBuilder MIB; local
2838 MachineInstrBuilder MIB = BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, local
[all...]
H A DMLxExpansionPass.cpp292 MachineInstrBuilder MIB = BuildMI(MBB, MI, MI->getDebugLoc(), MCID1, TmpReg) local
296 MIB.addImm(LaneImm);
297 MIB.addImm(Pred).addReg(PredReg);
299 MIB = BuildMI(MBB, MI, MI->getDebugLoc(), MCID2)
304 MIB.addReg(TmpReg, getKillRegState(true))
307 MIB.addReg(AccReg).addReg(TmpReg, getKillRegState(true));
309 MIB.addImm(Pred).addReg(PredReg);
H A DARMFrameLowering.cpp222 MachineInstrBuilder MIB = local
226 AddDefaultCC(AddDefaultPred(MIB));
445 MachineInstrBuilder MIB = BuildMI(MBB, MBBI, dl, TII.get(TCOpcode)); local
447 MIB.addGlobalAddress(JumpTarget.getGlobal(), JumpTarget.getOffset(),
451 MIB.addExternalSymbol(JumpTarget.getSymbolName(),
456 if (STI.isThumb()) MIB.addImm(ARMCC::AL).addReg(0);
626 MachineInstrBuilder MIB = local
630 MIB.addReg(Regs[i].first, getKillRegState(Regs[i].second));
632 MachineInstrBuilder MIB = BuildMI(MBB, MI, DL, TII.get(StrOpc), local
637 AddDefaultPred(MIB);
691 MachineInstrBuilder MIB = local
706 MachineInstrBuilder MIB = local
789 MachineInstrBuilder MIB = BuildMI(MBB, MI, DL, TII.get(Opc), ARM::SP) local
[all...]
H A DThumb2ITBlockPass.cpp181 MachineInstrBuilder MIB = BuildMI(MBB, MBBI, dl, TII->get(ARM::t2IT)) local
189 MachineBasicBlock::iterator InsertPos = MIB;
232 MIB.addImm(Mask);
H A DARMLoadStoreOptimizer.cpp349 MachineInstrBuilder MIB = BuildMI(MBB, MBBI, dl, TII->get(Opcode))
353 MIB = MIB.addReg(Regs[i].first, getDefRegState(isDef)
358 MIB.addReg(ImpDefs[i], RegState::ImplicitDefine);
777 MachineInstrBuilder MIB = BuildMI(MBB, MBBI, dl, TII->get(NewOpc)) local
784 MIB.addOperand(MI->getOperand(OpNum));
787 MIB->setMemRefs(MI->memoperands_begin(), MI->memoperands_end());
1082 MachineInstrBuilder MIB = BuildMI(MBB, MBBI, MBBI->getDebugLoc(), local
1086 MIB.addImm(Offset).addImm(Pred).addReg(PredReg);
1088 MachineInstrBuilder MIB local
1744 MachineInstrBuilder MIB = BuildMI(*MBB, InsertPos, dl, MCID) local
1758 MachineInstrBuilder MIB = BuildMI(*MBB, InsertPos, dl, MCID) local
[all...]
H A DThumb2InstrInfo.cpp279 MachineInstrBuilder MIB =
284 AddDefaultCC(MIB);
411 MachineInstrBuilder MIB(&MI);
412 AddDefaultPred(MIB);
/macosx-10.10/llvmCore-3425.0.34/lib/Target/Mips/
H A DMips16InstrInfo.cpp70 MachineInstrBuilder MIB = BuildMI(MBB, I, DL, get(Opc)); local
73 MIB.addReg(DestReg, RegState::Define);
76 MIB.addReg(ZeroReg);
79 MIB.addReg(SrcReg, getKillRegState(KillSrc));
H A DMipsInstrInfo.cpp68 MachineInstrBuilder MIB = BuildMI(MF, DL, get(Mips::DBG_VALUE)) local
70 return &*MIB;
179 MachineInstrBuilder MIB = BuildMI(&MBB, DL, MCID); local
183 MIB.addReg(Cond[i].getReg());
185 MIB.addImm(Cond[i].getImm());
189 MIB.addMBB(TBB);
H A DMipsSEInstrInfo.cpp142 MachineInstrBuilder MIB = BuildMI(MBB, I, DL, get(Opc)); local
145 MIB.addReg(DestReg, RegState::Define);
148 MIB.addReg(ZeroReg);
151 MIB.addReg(SrcReg, getKillRegState(KillSrc));
/macosx-10.10/llvmCore-3425.0.34/lib/CodeGen/
H A DMachineInstrBundle.cpp109 MachineInstrBuilder MIB = BuildMI(MBB, FirstMI, FirstMI->getDebugLoc(), local
190 MIB.addReg(Reg, getDefRegState(true) | getDeadRegState(isDead) |
199 MIB.addReg(Reg, getKillRegState(isKill) | getUndefRegState(isUndef) |
H A DMachineSSAUpdater.cpp190 MachineInstrBuilder MIB(InsertedPHI);
192 MIB.addReg(PredValues[i].second).addMBB(PredValues[i].first);
/macosx-10.10/llvmCore-3425.0.34/lib/CodeGen/SelectionDAG/
H A DInstrEmitter.cpp651 MachineInstrBuilder MIB = BuildMI(*MF, DL, II);
662 MIB.addReg(0U); // undef
664 AddOperand(&*MIB, Op, (*MIB).getNumOperands(), &II, VRBaseMap,
670 MIB.addCImm(CI);
672 MIB.addImm(CI->getSExtValue());
674 MIB.addFPImm(CF);
678 MIB.addReg(0U);
682 MIB.addReg(0U);
685 MIB
[all...]
/macosx-10.10/llvmCore-3425.0.34/lib/Target/MBlaze/
H A DMBlazeFrameLowering.cpp59 MachineInstr::mop_iterator MIB = MBB->operands_begin(); local
62 for (MachineInstr::mop_iterator MII = MIB; MII != MIE; ++MII) {
99 MachineBasicBlock::iterator MIB = MBB->begin(); local
121 for (MachineBasicBlock::iterator I=MIB; I != MIE; ++I) {
171 for (MachineBasicBlock::iterator I=MIB; I != MIE; ++I) {
/macosx-10.10/llvmCore-3425.0.34/lib/Target/XCore/
H A DXCoreInstrInfo.cpp393 MachineInstrBuilder MIB = BuildMI(MF, DL, get(XCore::DBG_VALUE)) local
395 return &*MIB;

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