Lines Matching refs:MIB
383 MachineInstrBuilder MIB = BuildMI(MBB, MBBI, MI.getDebugLoc(),
391 MIB.addReg(D0, RegState::Define | getDeadRegState(DstIsDead));
393 MIB.addReg(D1, RegState::Define | getDeadRegState(DstIsDead));
395 MIB.addReg(D2, RegState::Define | getDeadRegState(DstIsDead));
397 MIB.addReg(D3, RegState::Define | getDeadRegState(DstIsDead));
400 MIB.addOperand(MI.getOperand(OpIdx++));
403 MIB.addOperand(MI.getOperand(OpIdx++));
404 MIB.addOperand(MI.getOperand(OpIdx++));
407 MIB.addOperand(MI.getOperand(OpIdx++));
417 MIB.addOperand(MI.getOperand(OpIdx++));
418 MIB.addOperand(MI.getOperand(OpIdx++));
425 MIB.addOperand(MO);
428 MIB.addReg(DstReg, RegState::ImplicitDefine | getDeadRegState(DstIsDead));
429 TransferImpOps(MI, MIB, MIB);
432 MIB->setMemRefs(MI.memoperands_begin(), MI.memoperands_end());
448 MachineInstrBuilder MIB = BuildMI(MBB, MBBI, MI.getDebugLoc(),
452 MIB.addOperand(MI.getOperand(OpIdx++));
455 MIB.addOperand(MI.getOperand(OpIdx++));
456 MIB.addOperand(MI.getOperand(OpIdx++));
459 MIB.addOperand(MI.getOperand(OpIdx++));
466 MIB.addReg(D0, getUndefRegState(SrcIsUndef));
468 MIB.addReg(D1, getUndefRegState(SrcIsUndef));
470 MIB.addReg(D2, getUndefRegState(SrcIsUndef));
472 MIB.addReg(D3, getUndefRegState(SrcIsUndef));
475 MIB.addOperand(MI.getOperand(OpIdx++));
476 MIB.addOperand(MI.getOperand(OpIdx++));
479 MIB->addRegisterKilled(SrcReg, TRI, true);
480 TransferImpOps(MI, MIB, MIB);
483 MIB->setMemRefs(MI.memoperands_begin(), MI.memoperands_end());
500 MachineInstrBuilder MIB = BuildMI(MBB, MBBI, MI.getDebugLoc(),
522 MIB.addReg(D0, RegState::Define | getDeadRegState(DstIsDead));
524 MIB.addReg(D1, RegState::Define | getDeadRegState(DstIsDead));
526 MIB.addReg(D2, RegState::Define | getDeadRegState(DstIsDead));
528 MIB.addReg(D3, RegState::Define | getDeadRegState(DstIsDead));
532 MIB.addOperand(MI.getOperand(OpIdx++));
535 MIB.addOperand(MI.getOperand(OpIdx++));
536 MIB.addOperand(MI.getOperand(OpIdx++));
539 MIB.addOperand(MI.getOperand(OpIdx++));
549 MIB.addReg(D0, SrcFlags);
551 MIB.addReg(D1, SrcFlags);
553 MIB.addReg(D2, SrcFlags);
555 MIB.addReg(D3, SrcFlags);
558 MIB.addImm(Lane);
562 MIB.addOperand(MI.getOperand(OpIdx++));
563 MIB.addOperand(MI.getOperand(OpIdx++));
567 MIB.addOperand(MO);
570 MIB.addReg(DstReg, RegState::ImplicitDefine | getDeadRegState(DstIsDead));
571 TransferImpOps(MI, MIB, MIB);
573 MIB->setMemRefs(MI.memoperands_begin(), MI.memoperands_end());
584 MachineInstrBuilder MIB = BuildMI(MBB, MBBI, MI.getDebugLoc(), TII->get(Opc));
588 MIB.addOperand(MI.getOperand(OpIdx++));
590 MIB.addOperand(MI.getOperand(OpIdx++));
596 MIB.addReg(D0);
599 MIB.addOperand(MI.getOperand(OpIdx++));
602 MIB.addOperand(MI.getOperand(OpIdx++));
603 MIB.addOperand(MI.getOperand(OpIdx++));
606 MIB->addRegisterKilled(SrcReg, TRI, true);
607 TransferImpOps(MI, MIB, MIB);
841 MachineInstrBuilder MIB =
847 TransferImpOps(MI, MIB, MIB);
853 MachineInstrBuilder MIB =
858 MIB->setMemRefs(MI.memoperands_begin(), MI.memoperands_end());
859 TransferImpOps(MI, MIB, MIB);
945 MachineInstrBuilder MIB =
954 MIB.addOperand(MI.getOperand(OpIdx++));
957 MIB.addOperand(MI.getOperand(OpIdx++));
958 MIB.addOperand(MI.getOperand(OpIdx++));
963 MIB.addReg(D0, RegState::Define | getDeadRegState(DstIsDead))
967 MIB.addReg(DstReg, RegState::ImplicitDefine | getDeadRegState(DstIsDead));
968 TransferImpOps(MI, MIB, MIB);
969 MIB.setMemRefs(MI.memoperands_begin(), MI.memoperands_end());
976 MachineInstrBuilder MIB =
985 MIB.addOperand(MI.getOperand(OpIdx++));
988 MIB.addOperand(MI.getOperand(OpIdx++));
989 MIB.addOperand(MI.getOperand(OpIdx++));
994 MIB.addReg(D0).addReg(D1);
997 MIB->addRegisterKilled(SrcReg, TRI, true);
999 TransferImpOps(MI, MIB, MIB);
1000 MIB.setMemRefs(MI.memoperands_begin(), MI.memoperands_end());
1008 MachineInstrBuilder MIB =
1018 MIB.addOperand(MI.getOperand(OpIdx++));
1019 MIB.addReg(DReg);
1022 MIB.addImm(Lane);
1024 MIB.addOperand(MI.getOperand(OpIdx++));
1025 MIB.addOperand(MI.getOperand(OpIdx++));
1027 TransferImpOps(MI, MIB, MIB);
1236 MachineInstrBuilder MIB =
1241 MIB.addReg(DReg, RegState::Define); // Output DPR
1242 MIB.addReg(DReg); // Input DPR
1243 MIB.addOperand(MI.getOperand(2)); // Input GPR
1244 MIB.addImm(DLane); // Lane
1247 MIB.addOperand(MI.getOperand(4));
1248 MIB.addOperand(MI.getOperand(5));
1251 MIB->addRegisterKilled(QReg, TRI, true);
1254 MIB->addRegisterDefined(QReg, TRI);
1256 TransferImpOps(MI, MIB, MIB);