Searched refs:FSUB (Results 1 - 25 of 26) sorted by relevance

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/macosx-10.10/file_cmds-242/pax/
H A Dpax.h215 } FSUB; typedef in typeref:struct:__anon8934
H A Doptions.c107 const FSUB fsub[] = {
216 FSUB tmp;
417 n_fsub = sizeof(fsub)/sizeof(FSUB);
418 if ((frmt = (FSUB *)bsearch(&tmp, fsub, n_fsub, sizeof(FSUB),
425 for (i = 0; i < (sizeof(fsub)/sizeof(FSUB)); ++i)
1105 FSUB tmp;
1278 n_fsub = sizeof(fsub)/sizeof(FSUB);
1279 if ((frmt = (FSUB *)bsearch((void *)&tmp, (void *)fsub,
1280 n_fsub, sizeof(FSUB), c_frm
[all...]
H A Dextern.h195 extern const FSUB fsub[];
220 extern const FSUB *frmt;
H A Dpax.c78 const FSUB *frmt = NULL; /* archive format type */
H A Dar_subs.c820 const FSUB *orgfrmt;
/macosx-10.10/BerkeleyDB-21/db/java/src/com/sleepycat/asm/
H A DOpcodes.java195 int FSUB = 102; // - field in interface:Opcodes
/macosx-10.10/llvmCore-3425.0.34/include/llvm/CodeGen/
H A DISDOpcodes.h234 FADD, FSUB, FMUL, FMA, FDIV, FREM, enumerator in enum:llvm::ISD::NodeType
/macosx-10.10/cxxfilt-11/cxxfilt/opcodes/
H A Dm88k-dis.c184 {0x84003000,"fsub.sss ",{21,5,REG} ,{16,5,REG} ,{0,5,REG} , {5,1,PFLT,FSUB ,0,1,1,1,0,0,0,1,0,0,0,0} },
185 {0x84003080,"fsub.ssd ",{21,5,REG} ,{16,5,REG} ,{0,5,REG} , {6,2,PFLT,FSUB ,0,1,1,1,0,0,0,1,0,0,1,0} },
186 {0x84003200,"fsub.sds ",{21,5,REG} ,{16,5,REG} ,{0,5,REG} , {6,2,PFLT,FSUB ,0,1,1,1,0,0,0,1,0,1,0,0} },
187 {0x84003280,"fsub.sdd ",{21,5,REG} ,{16,5,REG} ,{0,5,REG} , {6,2,PFLT,FSUB ,0,1,1,1,0,0,0,1,0,1,1,0} },
188 {0x84003020,"fsub.dss ",{21,5,REG} ,{16,5,REG} ,{0,5,REG} , {6,2,PFLT,FSUB ,0,1,1,1,0,0,0,1,1,0,0,0} },
189 {0x840030a0,"fsub.dsd ",{21,5,REG} ,{16,5,REG} ,{0,5,REG} , {6,2,PFLT,FSUB ,0,1,1,1,0,0,0,1,1,0,1,0} },
190 {0x84003220,"fsub.dds ",{21,5,REG} ,{16,5,REG} ,{0,5,REG} , {6,2,PFLT,FSUB ,0,1,1,1,0,0,0,1,1,1,0,0} },
191 {0x840032a0,"fsub.ddd ",{21,5,REG} ,{16,5,REG} ,{0,5,REG} , {6,2,PFLT,FSUB ,0,1,1,1,0,0,0,1,1,1,1,0} },
/macosx-10.10/cxxfilt-11/cxxfilt/include/opcode/
H A Dm88k.h343 #define FSUB NOP +2 macro
/macosx-10.10/llvmCore-3425.0.34/lib/CodeGen/SelectionDAG/
H A DLegalizeVectorOps.cpp59 // Implements expansion for FNEG; falls back to UnrollVectorOp if FSUB
180 case ISD::FSUB:
585 if (TLI.isOperationLegalOrCustom(ISD::FSUB, Op.getValueType())) {
587 return DAG.getNode(ISD::FSUB, Op.getDebugLoc(), Op.getValueType(),
H A DSelectionDAGBuilder.cpp2634 visitBinary(I, ISD::FSUB);
3712 SDValue X = DAG.getNode(ISD::FSUB, dl, MVT::f32, t0, t1);
3850 SDValue LogOfMantissa = DAG.getNode(ISD::FSUB, dl, MVT::f32, t2,
3870 SDValue t3 = DAG.getNode(ISD::FSUB, dl, MVT::f32, t2,
3876 SDValue LogOfMantissa = DAG.getNode(ISD::FSUB, dl, MVT::f32, t6,
3898 SDValue t3 = DAG.getNode(ISD::FSUB, dl, MVT::f32, t2,
3904 SDValue t7 = DAG.getNode(ISD::FSUB, dl, MVT::f32, t6,
3910 SDValue LogOfMantissa = DAG.getNode(ISD::FSUB, dl, MVT::f32, t10,
3958 SDValue Log2ofMantissa = DAG.getNode(ISD::FSUB, dl, MVT::f32, t2,
3978 SDValue t3 = DAG.getNode(ISD::FSUB, d
[all...]
H A DSelectionDAGDumper.cpp177 case ISD::FSUB: return "fsub";
H A DLegalizeFloatTypes.cpp91 case ISD::FSUB: R = SoftenFloatRes_FSUB(N); break;
871 case ISD::FSUB: ExpandFloatRes_FSUB(N, Lo, Hi); break;
1389 DAG.getNode(ISD::FSUB, dl,
H A DSelectionDAG.cpp2667 if (getTarget().Options.UnsafeFPMath && OpOpcode == ISD::FSUB)
2668 return getNode(ISD::FSUB, DL, VT, Operand.getNode()->getOperand(1),
2803 case ISD::FSUB:
2817 } else if (Opcode == ISD::FSUB) {
3064 case ISD::FSUB:
3111 case ISD::FSUB:
3150 case ISD::FSUB:
H A DLegalizeDAG.cpp2145 SDValue Sub = DAG.getNode(ISD::FSUB, dl, MVT::f64, Load, Bias);
2183 SDValue HiSub = DAG.getNode(ISD::FSUB, dl, MVT::f64, HiFlt,
2813 DAG.getNode(ISD::FSUB, dl, VT,
3017 Tmp1 = DAG.getNode(ISD::FSUB, dl, Node->getValueType(0), Tmp1,
3137 case ISD::FSUB: {
H A DDAGCombiner.cpp419 !TLI.isOperationLegalOrCustom(ISD::FSUB, Op.getValueType()))
429 case ISD::FSUB:
482 return DAG.getNode(ISD::FSUB, Op.getDebugLoc(), Op.getValueType(),
487 return DAG.getNode(ISD::FSUB, Op.getDebugLoc(), Op.getValueType(),
491 case ISD::FSUB:
501 return DAG.getNode(ISD::FSUB, Op.getDebugLoc(), Op.getValueType(),
1137 case ISD::FSUB: return visitFSUB(N);
5674 if ((!LegalOperations || TLI.isOperationLegalOrCustom(ISD::FSUB, VT)) &&
5676 return DAG.getNode(ISD::FSUB, N->getDebugLoc(), VT, N0,
5679 if ((!LegalOperations || TLI.isOperationLegalOrCustom(ISD::FSUB, V
[all...]
H A DLegalizeVectorTypes.cpp104 case ISD::FSUB:
537 case ISD::FSUB:
1312 case ISD::FSUB:
H A DFastISel.cpp952 return SelectBinaryOp(I, ISD::FSUB);
/macosx-10.10/vim-55/runtime/syntax/
H A Dtasm.vim54 syn keyword tasmCoprocInstr FSTP9 FSUB FSUBP FSUBR FSUBRP FTST FUCOM FUCOMI
H A Dmasm.vim236 syn keyword masmOpFloat FNSTCW FSTENV FNSTENV FSTP FSTSW FNSTSW FSUB
H A Dnasm.vim358 syn keyword nasmFpuInstruction FSTCW FSTENV FST[P] FSTSW FSUB[P] FSUBR[P]
/macosx-10.10/llvmCore-3425.0.34/lib/Target/CellSPU/
H A DSPUISelDAGToDAG.cpp790 if (Op0.getOpcode() == ISD::FSUB) {
/macosx-10.10/llvmCore-3425.0.34/lib/Target/PowerPC/
H A DPPCISelLowering.cpp3845 Cmp = DAG.getNode(ISD::FSUB, dl, CmpVT, LHS, RHS);
3851 Cmp = DAG.getNode(ISD::FSUB, dl, CmpVT, LHS, RHS);
3857 Cmp = DAG.getNode(ISD::FSUB, dl, CmpVT, RHS, LHS);
3863 Cmp = DAG.getNode(ISD::FSUB, dl, CmpVT, RHS, LHS);
/macosx-10.10/llvmCore-3425.0.34/lib/Target/ARM/
H A DARMFastISel.cpp1825 case ISD::FSUB:
2727 return SelectBinaryFPOp(I, ISD::FSUB);
/macosx-10.10/llvmCore-3425.0.34/lib/Target/X86/
H A DX86ISelLowering.cpp727 setOperationAction(ISD::FSUB, (MVT::SimpleValueType)VT, Expand);
834 setOperationAction(ISD::FSUB, MVT::v4f32, Legal);
868 setOperationAction(ISD::FSUB, MVT::v2f64, Legal);
1034 setOperationAction(ISD::FSUB, MVT::v8f32, Legal);
1043 setOperationAction(ISD::FSUB, MVT::v4f64, Legal);
1236 setTargetDAGCombine(ISD::FSUB);
7934 SDValue Sub = DAG.getNode(ISD::FSUB, dl, MVT::v2f64, XR2F, CLod1);
7985 SDValue Sub = DAG.getNode(ISD::FSUB, dl, MVT::f64, Or, Bias);
16264 case ISD::FSUB: return PerformFSUBCombine(N, DAG, Subtarget);

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