Searched refs:Amt (Results 1 - 19 of 19) sorted by relevance

/macosx-10.10/llvmCore-3425.0.34/lib/Target/ARM/MCTargetDesc/
H A DARMAddressingModes.h86 static inline unsigned rotr32(unsigned Val, unsigned Amt) { argument
87 assert(Amt < 32 && "Invalid rotate amount");
88 return (Val >> Amt) | (Val << ((32-Amt)&31));
93 static inline unsigned rotl32(unsigned Val, unsigned Amt) { argument
94 assert(Amt < 32 && "Invalid rotate amount");
95 return (Val << Amt) | (Val >> ((32-Amt)&31));
/macosx-10.10/llvmCore-3425.0.34/include/llvm/ADT/
H A DAPSInt.h114 APSInt operator>>(unsigned Amt) const {
115 return IsUnsigned ? APSInt(lshr(Amt), true) : APSInt(ashr(Amt), false);
117 APSInt& operator>>=(unsigned Amt) { argument
118 *this = *this >> Amt;
158 APSInt& operator<<=(unsigned Amt) { argument
159 *this = *this << Amt;
H A DAPInt.h871 APInt sshl_ov(unsigned Amt, bool &Overflow) const;
/macosx-10.10/llvmCore-3425.0.34/include/llvm/
H A DBasicBlock.h277 void AdjustBlockAddressRefCount(int Amt) { argument
278 setValueSubclassData(getSubclassDataFromValue()+Amt);
/macosx-10.10/llvmCore-3425.0.34/lib/CodeGen/SelectionDAG/
H A DLegalizeIntegerTypes.cpp1264 /// and the shift amount is a constant 'Amt'. Expand the operation.
1265 void DAGTypeLegalizer::ExpandShiftByConstant(SDNode *N, unsigned Amt, argument
1278 if (Amt > VTBits) {
1280 } else if (Amt > NVTBits) {
1283 NVT, InL, DAG.getConstant(Amt-NVTBits, ShTy));
1284 } else if (Amt == NVTBits) {
1287 } else if (Amt == 1 &&
1297 Lo = DAG.getNode(ISD::SHL, DL, NVT, InL, DAG.getConstant(Amt, ShTy));
1300 DAG.getConstant(Amt, ShTy)),
1302 DAG.getConstant(NVTBits-Amt, ShT
1358 SDValue Amt = N->getOperand(1); local
1446 SDValue Amt = N->getOperand(1); local
[all...]
H A DLegalizeTypes.h342 void ExpandShiftByConstant(SDNode *N, unsigned Amt,
H A DDAGCombiner.cpp250 SDValue visitShiftByConstant(SDNode *N, unsigned Amt);
3446 SDValue DAGCombiner::visitShiftByConstant(SDNode *N, unsigned Amt) { argument
3716 SDValue Amt = DAG.getConstant(ShiftAmt, local
3719 N0.getOperand(0), Amt);
3762 SDValue Amt = local
3766 N0.getOperand(0).getOperand(0), Amt);
4960 unsigned Amt = RHSC->getZExtValue(); local
4963 if (Amt >= Mask.getBitWidth()) break;
4964 APInt NewMask = Mask << Amt;
H A DTargetLowering.cpp3307 SDValue Amt = DAG.getConstant(ShAmt, getShiftAmountTy(Op1.getValueType())); local
3308 Op1 = DAG.getNode(ISD::SRA, dl, Op1.getValueType(), Op1, Amt);
H A DSelectionDAGBuilder.cpp3185 unsigned Amt = ElementSize.logBase2(); local
3188 DAG.getConstant(Amt, IdxN.getValueType()));
/macosx-10.10/llvmCore-3425.0.34/lib/Transforms/InstCombine/
H A DInstCombineCasts.cpp120 Value *Amt = 0; local
122 Amt = NumElements;
124 Amt = ConstantInt::get(AI.getArraySize()->getType(), Scale);
126 Amt = AllocaBuilder.CreateMul(Amt, NumElements);
132 Amt = AllocaBuilder.CreateAdd(Amt, Off);
135 AllocaInst *New = AllocaBuilder.CreateAlloca(CastElTy, Amt);
698 if (ConstantInt *Amt = dyn_cast<ConstantInt>(I->getOperand(1))) {
701 BitsToClear += Amt
[all...]
/macosx-10.10/llvmCore-3425.0.34/lib/Target/ARM/InstPrinter/
H A DARMInstPrinter.cpp585 unsigned Amt = ShiftOp & 0x1f; local
587 O << ", asr #" << (Amt == 0 ? 32 : Amt);
588 else if (Amt)
589 O << ", lsl #" << Amt; local
/macosx-10.10/llvmCore-3425.0.34/lib/Target/PowerPC/
H A DPPCISelLowering.cpp4034 SDValue Amt = Op.getOperand(2); local
4035 EVT AmtVT = Amt.getValueType();
4038 DAG.getConstant(BitWidth, AmtVT), Amt);
4039 SDValue Tmp2 = DAG.getNode(PPCISD::SHL, dl, VT, Hi, Amt);
4042 SDValue Tmp5 = DAG.getNode(ISD::ADD, dl, AmtVT, Amt,
4046 SDValue OutLo = DAG.getNode(PPCISD::SHL, dl, VT, Lo, Amt);
4063 SDValue Amt = Op.getOperand(2); local
4064 EVT AmtVT = Amt.getValueType();
4067 DAG.getConstant(BitWidth, AmtVT), Amt);
4068 SDValue Tmp2 = DAG.getNode(PPCISD::SRL, dl, VT, Lo, Amt);
4091 SDValue Amt = Op.getOperand(2); local
4163 BuildVSLDOI(SDValue LHS, SDValue RHS, unsigned Amt, EVT VT, SelectionDAG &DAG, DebugLoc dl) argument
[all...]
/macosx-10.10/llvmCore-3425.0.34/lib/VMCore/
H A DConstantFold.cpp248 ConstantInt *Amt = dyn_cast<ConstantInt>(CE->getOperand(1)); local
249 if (Amt == 0)
251 unsigned ShAmt = Amt->getZExtValue();
270 ConstantInt *Amt = dyn_cast<ConstantInt>(CE->getOperand(1)); local
271 if (Amt == 0)
273 unsigned ShAmt = Amt->getZExtValue();
H A DInstructions.cpp800 static Value *getAISize(LLVMContext &Context, Value *Amt) { argument
801 if (!Amt)
802 Amt = ConstantInt::get(Type::getInt32Ty(Context), 1);
804 assert(!isa<BasicBlock>(Amt) &&
806 assert(Amt->getType()->isIntegerTy() &&
809 return Amt;
/macosx-10.10/llvmCore-3425.0.34/lib/Target/ARM/
H A DARMBaseInstrInfo.cpp167 unsigned Amt = ARM_AM::getAM2Offset(OffImm); local
169 if (ARM_AM::getSOImmVal(Amt) == -1)
175 .addReg(BaseReg).addImm(Amt)
177 } else if (Amt != 0) {
179 unsigned SOOpc = ARM_AM::getSORegOpc(ShOpc, Amt);
193 unsigned Amt = ARM_AM::getAM3Offset(OffImm); local
198 .addReg(BaseReg).addImm(Amt)
/macosx-10.10/llvmCore-3425.0.34/lib/Target/ARM/AsmParser/
H A DARMAsmParser.cpp6913 unsigned Amt = Inst.getOperand(2).getImm(); local
6914 unsigned Opc = Amt == 0 ? ARM::MOVr : ARM::MOVsi;
6916 if (Amt == 32 && (ShiftTy == ARM_AM::lsr || ShiftTy == ARM_AM::asr))
6917 Amt = 0;
6918 unsigned Shifter = ARM_AM::getSORegOpc(ShiftTy, Amt);
/macosx-10.10/llvmCore-3425.0.34/lib/Target/X86/
H A DX86ISelLowering.cpp10803 SDValue Amt = Op.getOperand(1); local
10810 if (isSplatVector(Amt.getNode())) {
10811 SDValue SclrAmt = Amt->getOperand(0);
10862 SDValue Res = DAG.getNode(ISD::SRL, dl, VT, R, Amt);
10906 SDValue Res = DAG.getNode(ISD::SRL, dl, VT, R, Amt);
10994 if (Amt.getOpcode() == ISD::BUILD_VECTOR) {
10999 Amt1Csts.push_back(Amt->getOperand(i));
11001 Amt2Csts.push_back(Amt->getOperand(i));
11009 Amt1 = Extract128BitVector(Amt, 0, DAG, dl);
11010 Amt2 = Extract128BitVector(Amt, NumElem
[all...]
H A DX86InstrInfo.cpp2146 unsigned Amt = MI->getOperand(3).getImm(); local
2153 MI->getOperand(3).setImm(Size-Amt);
/macosx-10.10/llvmCore-3425.0.34/lib/Analysis/
H A DScalarEvolution.cpp3786 uint64_t Amt = BitWidth - CI->getZExtValue();
3787 if (Amt == BitWidth)
3792 Amt)),

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