Searched refs:trng (Results 1 - 20 of 20) sorted by relevance

/linux-master/drivers/crypto/hisilicon/trng/
H A DMakefile1 obj-$(CONFIG_CRYPTO_DEV_HISI_TRNG) += hisi-trng-v2.o
2 hisi-trng-v2-objs = trng.o
H A Dtrng.c61 struct hisi_trng *trng; member in struct:hisi_trng_ctx
67 static void hisi_trng_set_seed(struct hisi_trng *trng, const u8 *seed) argument
79 writel(val, trng->base + SW_DRBG_SEED(seed_reg));
87 struct hisi_trng *trng = ctx->trng; local
92 pr_err("slen(%u) is not matched with trng(%d)\n", slen,
97 writel(0x0, trng->base + SW_DRBG_BLOCKS);
98 hisi_trng_set_seed(trng, seed);
101 trng->base + SW_DRBG_BLOCKS);
102 writel(0x1, trng
116 struct hisi_trng *trng = ctx->trng; local
157 struct hisi_trng *trng; local
185 struct hisi_trng *trng; local
229 hisi_trng_add_to_list(struct hisi_trng *trng) argument
236 hisi_trng_del_from_list(struct hisi_trng *trng) argument
252 struct hisi_trng *trng; local
308 struct hisi_trng *trng = platform_get_drvdata(pdev); local
[all...]
/linux-master/drivers/char/hw_random/
H A Dxiphera-trng.c24 /* trng statuses */
37 struct xiphera_trng *trng = container_of(rng, struct xiphera_trng, rng); local
42 if (readl(trng->mem + STATUS_REG) == TRNG_NEW_RAND_AVAILABLE) {
43 *(u32 *)buf = readl(trng->mem + RAND_REG);
45 * Inform the trng of the read
48 writel(HOST_TO_TRNG_READ, trng->mem + CONTROL_REG);
49 writel(HOST_TO_TRNG_ENABLE, trng->mem + CONTROL_REG);
63 struct xiphera_trng *trng; local
66 trng = devm_kzalloc(dev, sizeof(*trng), GFP_KERNE
[all...]
H A Djh7110-trng.c24 /* trng register offset */
123 static inline int starfive_trng_wait_idle(struct starfive_trng *trng) argument
127 return readl_relaxed_poll_timeout(trng->base + STARFIVE_STAT, stat,
133 static inline void starfive_trng_irq_mask_clear(struct starfive_trng *trng) argument
136 u32 data = readl(trng->base + STARFIVE_ISTAT);
138 writel(data, trng->base + STARFIVE_ISTAT);
141 static int starfive_trng_cmd(struct starfive_trng *trng, u32 cmd, bool wait) argument
151 reinit_completion(&trng->random_done);
152 spin_lock_irq(&trng->write_lock);
153 writel(cmd, trng
175 struct starfive_trng *trng = to_trng(rng); local
210 struct starfive_trng *trng = (struct starfive_trng *)priv; local
236 struct starfive_trng *trng = to_trng(rng); local
247 struct starfive_trng *trng = to_trng(rng); local
278 struct starfive_trng *trng; local
354 struct starfive_trng *trng = dev_get_drvdata(dev); local
364 struct starfive_trng *trng = dev_get_drvdata(dev); local
[all...]
H A Dingenic-trng.c37 struct ingenic_trng *trng = container_of(rng, struct ingenic_trng, rng); local
40 ctrl = readl(trng->base + TRNG_REG_CFG_OFFSET);
42 writel(ctrl, trng->base + TRNG_REG_CFG_OFFSET);
49 struct ingenic_trng *trng = container_of(rng, struct ingenic_trng, rng); local
52 ctrl = readl(trng->base + TRNG_REG_CFG_OFFSET);
54 writel(ctrl, trng->base + TRNG_REG_CFG_OFFSET);
59 struct ingenic_trng *trng = container_of(rng, struct ingenic_trng, rng); local
64 ret = readl_poll_timeout(trng->base + TRNG_REG_STATUS_OFFSET, status,
71 *data = readl(trng->base + TRNG_REG_RANDOMNUM_OFFSET);
78 struct ingenic_trng *trng; local
[all...]
H A Datmel-rng.c43 static bool atmel_trng_wait_ready(struct atmel_trng *trng, bool wait) argument
47 ready = readl(trng->base + TRNG_ISR) & TRNG_ISR_DATRDY;
49 readl_poll_timeout(trng->base + TRNG_ISR, ready,
58 struct atmel_trng *trng = container_of(rng, struct atmel_trng, rng); local
62 ret = pm_runtime_get_sync((struct device *)trng->rng.priv);
64 pm_runtime_put_sync((struct device *)trng->rng.priv);
68 ret = atmel_trng_wait_ready(trng, wait);
72 *data = readl(trng->base + TRNG_ODATA);
78 readl(trng->base + TRNG_ISR);
82 pm_runtime_mark_last_busy((struct device *)trng
87 atmel_trng_init(struct atmel_trng *trng) argument
109 atmel_trng_cleanup(struct atmel_trng *trng) argument
117 struct atmel_trng *trng; local
166 struct atmel_trng *trng = platform_get_drvdata(pdev); local
175 struct atmel_trng *trng = dev_get_drvdata(dev); local
184 struct atmel_trng *trng = dev_get_drvdata(dev); local
[all...]
H A Dexynos-trng.c58 struct exynos_trng_dev *trng; local
63 trng = (struct exynos_trng_dev *)rng->priv;
65 writel_relaxed(max * 8, trng->mem + EXYNOS_TRNG_FIFO_CTRL);
66 val = readl_poll_timeout(trng->mem + EXYNOS_TRNG_FIFO_CTRL, val,
71 memcpy_fromio(data, trng->mem + EXYNOS_TRNG_FIFO_0, max);
78 struct exynos_trng_dev *trng = (struct exynos_trng_dev *)rng->priv; local
82 sss_rate = clk_get_rate(trng->clk);
90 dev_err(trng->dev, "clock divider too large: %d", val);
94 writel_relaxed(val, trng->mem + EXYNOS_TRNG_CLKDIV);
98 writel_relaxed(val, trng
111 struct exynos_trng_dev *trng; local
178 struct exynos_trng_dev *trng = platform_get_drvdata(pdev); local
[all...]
H A Darm_smccc_trng.c99 struct hwrng *trng; local
101 trng = devm_kzalloc(&pdev->dev, sizeof(*trng), GFP_KERNEL);
102 if (!trng)
105 trng->name = "smccc_trng";
106 trng->read = smccc_trng_read;
108 return devm_hwrng_register(&pdev->dev, trng);
H A DMakefile17 obj-$(CONFIG_HW_RANDOM_EXYNOS) += exynos-trng.o
26 obj-$(CONFIG_HW_RANDOM_INGENIC_TRNG) += ingenic-trng.o
42 obj-$(CONFIG_HW_RANDOM_S390) += s390-trng.o
47 obj-$(CONFIG_HW_RANDOM_XIPHERA) += xiphera-trng.o
51 obj-$(CONFIG_HW_RANDOM_JH7110) += jh7110-trng.o
/linux-master/drivers/crypto/amcc/
H A Dcrypto4xx_trng.c74 struct device_node *trng = NULL; local
79 trng = of_find_matching_node(NULL, ppc4xx_trng_match);
80 if (!trng || !of_device_is_available(trng)) {
81 of_node_put(trng);
85 dev->trng_base = of_iomap(trng, 0);
86 of_node_put(trng);
98 core_dev->trng = rng;
101 err = devm_hwrng_register(core_dev->device, core_dev->trng);
114 core_dev->trng
[all...]
H A Dcrypto4xx_core.h110 struct hwrng *trng; member in struct:crypto4xx_core_device
/linux-master/drivers/crypto/gemini/
H A Dsl3516-ce-rng.c20 ce = container_of(rng, struct sl3516_ce_dev, trng);
48 ce->trng.name = "SL3516 Crypto Engine RNG";
49 ce->trng.read = sl3516_ce_rng_read;
50 ce->trng.quality = 700;
52 ret = hwrng_register(&ce->trng);
60 hwrng_unregister(&ce->trng);
H A Dsl3516-ce.h216 * @trng hw_random structure for RNG
243 struct hwrng trng; member in struct:sl3516_ce_dev
/linux-master/drivers/crypto/allwinner/sun8i-ce/
H A Dsun8i-ce-trng.c3 * sun8i-ce-trng.c - hardware cryptographic offloader for
35 ce = container_of(rng, struct sun8i_ce_dev, trng);
68 common = ce->variant->trng | CE_COMM_INT;
105 if (ce->variant->trng == CE_ID_NOTSUPP) {
109 ce->trng.name = "sun8i Crypto Engine TRNG";
110 ce->trng.read = sun8i_ce_trng_read;
112 ret = hwrng_register(&ce->trng);
120 if (ce->variant->trng == CE_ID_NOTSUPP)
122 hwrng_unregister(&ce->trng);
H A DMakefile5 sun8i-ce-$(CONFIG_CRYPTO_DEV_SUN8I_CE_TRNG) += sun8i-ce-trng.o
H A Dsun8i-ce.h142 * @trng: The CE_ALG_XXX value for the TRNG
155 unsigned char trng; member in struct:ce_variant
236 struct hwrng trng; member in struct:sun8i_ce_dev
H A Dsun8i-ce-core.c53 .trng = CE_ID_NOTSUPP,
70 .trng = CE_ID_NOTSUPP,
92 .trng = CE_ALG_TRNG_V2,
109 .trng = CE_ID_NOTSUPP,
124 { "trng", 0, 0 },
128 .trng = CE_ALG_TRNG,
145 .trng = CE_ID_NOTSUPP,
/linux-master/drivers/crypto/hisilicon/
H A DMakefile8 obj-$(CONFIG_CRYPTO_DEV_HISI_TRNG) += trng/
/linux-master/arch/arm64/kvm/
H A DMakefile17 arch_timer.o trng.o vmid.o emulate-nested.o nested.o \
/linux-master/drivers/crypto/caam/
H A Dregs.h297 u32 trng; /* TRNG_VERSION */ member in struct:version_regs

Completed in 181 milliseconds