| /linux-master/drivers/hid/intel-ish-hid/ |
| H A D | Makefile | 16 obj-$(CONFIG_INTEL_ISH_HID) += intel-ish-ipc.o
17 intel-ish-ipc-objs := ipc/ipc.o
18 intel-ish-ipc-objs += ipc/pci-ish.o
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| /linux-master/arch/arm64/kvm/hyp/nvhe/ |
| H A D | tlb.c | 36 * being either ish or nsh, depending on the invalidation
51 dsb(ish);
170 dsb(ish);
172 dsb(ish);
227 dsb(ish);
229 dsb(ish);
243 dsb(ish);
267 dsb(ish);
269 dsb(ish);
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| /linux-master/arch/arm/include/asm/ |
| H A D | switch_to.h | 15 #define __complete_pending_tlbi() dsb(ish)
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| H A D | barrier.h | 77 #define __smp_mb() dmb(ish)
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| H A D | tlbflush.h | 355 dsb(ish);
409 dsb(ish);
469 dsb(ish);
519 dsb(ish);
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| H A D | assembler.h | 381 ALT_SMP(dmb ish)
383 ALT_SMP(W(dmb) ish)
404 dmb ish
406 W(dmb) ish
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| /linux-master/arch/arm64/kvm/hyp/vhe/ |
| H A D | tlb.c | 116 dsb(ish);
118 dsb(ish);
177 dsb(ish);
179 dsb(ish);
195 dsb(ish);
220 dsb(ish);
|
| /linux-master/arch/arm64/include/asm/vdso/ |
| H A D | compat_barrier.h | 23 #define aarch32_smp_mb() dmb(ish)
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| /linux-master/arch/arm64/include/asm/ |
| H A D | atomic_ll_sc.h | 86 ATOMIC_OP_RETURN( , dmb ish, , l, "memory", __VA_ARGS__)\
90 ATOMIC_FETCH_OP ( , dmb ish, , l, "memory", __VA_ARGS__)\
101 ATOMIC_FETCH_OP ( , dmb ish, , l, "memory", __VA_ARGS__)\
182 ATOMIC64_OP_RETURN(, dmb ish, , l, "memory", __VA_ARGS__) \
186 ATOMIC64_FETCH_OP (, dmb ish, , l, "memory", __VA_ARGS__) \
197 ATOMIC64_FETCH_OP (, dmb ish, , l, "memory", __VA_ARGS__) \
230 " dmb ish\n"
290 __CMPXCHG_CASE(w, b, mb_, 8, dmb ish, , l, "memory", K)
291 __CMPXCHG_CASE(w, h, mb_, 16, dmb ish, , l, "memory", K)
292 __CMPXCHG_CASE(w, , mb_, 32, dmb ish, ,
[all...] |
| H A D | tlbflush.h | 35 "dsb ish\n tlbi " #op, \
43 "dsb ish\n tlbi " #op ", %0", \
269 dsb(ish);
281 dsb(ish);
308 dsb(ish);
316 * will have two consecutive TLBI instructions with a dsb(ish) in between
317 * defeating the purpose (i.e save overall 'dsb ish' cost).
339 dsb(ish);
354 dsb(ish);
478 dsb(ish);
[all...] |
| H A D | cacheflush.h | 139 dsb(ish);
|
| H A D | cmpxchg.h | 57 __XCHG_CASE(w, b, mb_, 8, dmb ish, nop, , a, l, "memory")
58 __XCHG_CASE(w, h, mb_, 16, dmb ish, nop, , a, l, "memory")
59 __XCHG_CASE(w, , mb_, 32, dmb ish, nop, , a, l, "memory")
60 __XCHG_CASE( , , mb_, 64, dmb ish, nop, , a, l, "memory")
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| H A D | barrier.h | 123 #define __smp_mb() dmb(ish)
|
| /linux-master/arch/arm64/kernel/ |
| H A D | hibernate-asm.S | 82 dsb ish /* wait for PoU cleaning to finish */
88 dsb ish
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| H A D | sys_compat.c | 40 dsb(ish);
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| /linux-master/arch/arm/mm/ |
| H A D | tlb-v7.S | 38 dsb ish
59 dsb ish
72 dsb ish
87 dsb ish
|
| /linux-master/drivers/hid/intel-ish-hid/ishtp/ |
| H A D | bus.h | 12 #include <linux/intel-ish-client-if.h>
|
| H A D | ishtp-dev.h | 13 #include <linux/intel-ish-client-if.h>
|
| /linux-master/tools/virtio/asm/ |
| H A D | barrier.h | 24 #define virt_store_mb(var, value) do { WRITE_ONCE(var, value); dmb(ish); } while (0)
|
| /linux-master/arch/arm64/mm/ |
| H A D | cache.S | 35 dcache_by_line_op cvau, ish, x2, x3, x4, x5, \fixup
131 dcache_by_line_op cvau, ish, x0, x1, x2, x3
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| /linux-master/arch/arm/kernel/ |
| H A D | smp_tlb.c | 83 dsb(ish);
90 dsb(ish);
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| /linux-master/drivers/firmware/efi/libstub/ |
| H A D | arm64.c | 114 dsb(ish);
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| /linux-master/drivers/media/pci/intel/ipu6/ |
| H A D | ipu6-buttress.h | 49 struct ipu6_buttress_ipc ish; member in struct:ipu6_buttress
|
| H A D | ipu6-buttress.c | 229 ipc = ipc_domain == IPU6_BUTTRESS_IPC_CSE ? &b->cse : &b->ish;
387 ipu6_buttress_ipc_recv(isp, &b->ish, &b->ish.recv_data);
388 complete(&b->ish.recv_complete);
400 complete(&b->ish.send_complete);
836 init_completion(&b->ish.send_complete);
838 init_completion(&b->ish.recv_complete);
851 memset(&b->ish, 0, sizeof(b->ish));
|
| /linux-master/drivers/hid/ |
| H A D | Makefile | 168 obj-$(CONFIG_INTEL_ISH_HID) += intel-ish-hid/
169 obj-$(INTEL_ISH_FIRMWARE_DOWNLOADER) += intel-ish-hid/
|