Searched refs:fixed_div (Results 1 - 15 of 15) sorted by relevance

/linux-master/drivers/clk/socfpga/
H A Dclk-gate-a10.c27 if (socfpgaclk->fixed_div)
28 div = socfpgaclk->fixed_div;
47 u32 fixed_div; local
71 rc = of_property_read_u32(node, "fixed-divider", &fixed_div);
73 socfpga_clk->fixed_div = 0;
75 socfpga_clk->fixed_div = fixed_div;
H A Dclk-periph-a10.c26 if (socfpgaclk->fixed_div) {
27 div = socfpgaclk->fixed_div;
70 u32 fixed_div; local
90 rc = of_property_read_u32(node, "fixed-divider", &fixed_div);
92 periph_clk->fixed_div = 0;
94 periph_clk->fixed_div = fixed_div;
H A Dclk-periph.c23 if (socfpgaclk->fixed_div) {
24 div = socfpgaclk->fixed_div;
60 u32 fixed_div; local
80 rc = of_property_read_u32(node, "fixed-divider", &fixed_div);
82 periph_clk->fixed_div = 0;
84 periph_clk->fixed_div = fixed_div;
H A Dclk.h46 u32 fixed_div; member in struct:socfpga_gate_clk
58 u32 fixed_div; member in struct:socfpga_periph_clk
H A Dclk-gate.c94 if (socfpgaclk->fixed_div)
95 div = socfpgaclk->fixed_div;
141 u32 fixed_div; local
170 rc = of_property_read_u32(node, "fixed-divider", &fixed_div);
172 socfpga_clk->fixed_div = 0;
174 socfpga_clk->fixed_div = fixed_div;
H A Dclk-gate-s10.c27 if (socfpgaclk->fixed_div) {
28 div = socfpgaclk->fixed_div;
145 socfpga_clk->fixed_div = clks->fixed_div;
203 socfpga_clk->fixed_div = clks->fixed_div;
H A Dstratix10-clk.h73 u8 fixed_div; member in struct:stratix10_gate_clock
H A Dclk-periph-s10.c53 if (socfpgaclk->fixed_div) {
54 div = socfpgaclk->fixed_div;
196 periph_clk->fixed_div = clks->fixed_divider;
/linux-master/drivers/clk/renesas/
H A Drcar-gen3-cpg.c157 * clk->rate = (parent->rate * mult / 32 ) / fixed_div
169 unsigned int fixed_div; member in struct:cpg_z_clk
186 32 * zclk->fixed_div);
205 prate * zclk->fixed_div);
207 prate = req->best_parent_rate / zclk->fixed_div;
227 mult = DIV64_U64_ROUND_CLOSEST(rate * 32ULL * zclk->fixed_div,
293 zclk->fixed_div = div; /* PLLVCO x 1/div x SYS-CPU divider */
302 zclk->fixed_div;
H A Drcar-gen4-cpg.c190 unsigned int fixed_div; member in struct:cpg_z_clk
207 32 * zclk->fixed_div);
226 prate * zclk->fixed_div);
228 prate = req->best_parent_rate / zclk->fixed_div;
248 mult = DIV64_U64_ROUND_CLOSEST(rate * 32ULL * zclk->fixed_div,
317 zclk->fixed_div = div; /* PLLVCO x 1/div x SYS-CPU divider */
326 zclk->fixed_div;
/linux-master/arch/arm/mach-omap1/
H A Dclock.h73 * @fixed_div: when > 0, this clock's rate is its parent's rate / @fixed_div
89 u8 fixed_div; member in struct:omap1_clk
H A Dclock.c808 WARN_ON(!clk->fixed_div);
810 return p_rate / clk->fixed_div;
H A Dclock_data.c182 .fixed_div = 14,
/linux-master/drivers/clk/qcom/
H A Dgcc-ipq4019.c62 * @fixed_div: fixed divider value if divider is fixed
71 u32 fixed_div; member in struct:clk_fepll
266 if (pll->fixed_div) {
267 pre_div = pll->fixed_div;
289 .fixed_div = 28,
305 .fixed_div = 32,
321 .fixed_div = 32,
337 .fixed_div = 20,
353 .fixed_div = 8,
/linux-master/include/linux/clk/
H A Dti.h170 u8 fixed_div; member in struct:clk_hw_omap

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