Searched refs:TARGET_QSYS (Results 1 - 4 of 4) sorted by relevance

/linux-master/drivers/net/ethernet/microchip/lan966x/
H A Dlan966x_regs.h25 TARGET_QSYS = 46, enumerator in enum:lan966x_target
1272 #define QSYS_PORT_MODE(r) __REG(TARGET_QSYS, 0, 1, 28008, 0, 1, 216, 0, r, 10, 4)
1281 #define QSYS_SW_PORT_MODE(r) __REG(TARGET_QSYS, 0, 1, 28008, 0, 1, 216, 80, r, 9, 4)
1314 #define QSYS_SW_STATUS(r) __REG(TARGET_QSYS, 0, 1, 28008, 0, 1, 216, 164, r, 9, 4)
1323 #define QSYS_CPU_GROUP_MAP __REG(TARGET_QSYS, 0, 1, 28008, 0, 1, 216, 204, 0, 1, 4)
1326 #define QSYS_RES_CFG(g) __REG(TARGET_QSYS, 0, 1, 32768, g, 1024, 8, 0, 0, 1, 4)
1329 #define QSYS_CIR_CFG(g) __REG(TARGET_QSYS, 0, 1, 16384, g, 90, 128, 0, 0, 1, 4)
1344 #define QSYS_SE_CFG(g) __REG(TARGET_QSYS, 0, 1, 16384, g, 90, 128, 8, 0, 1, 4)
1370 #define QSYS_SE_DWRR_CFG(g, r) __REG(TARGET_QSYS, 0, 1, 16384, g, 90, 128, 12, r, 12, 4)
1379 #define QSYS_TAS_CFG_CTRL __REG(TARGET_QSYS,
[all...]
H A Dlan966x_main.c62 { TARGET_QSYS, 0x100000, 1 }, /* 0xe2100000 */
/linux-master/drivers/net/ethernet/microchip/sparx5/
H A Dsparx5_main_regs.h48 TARGET_QSYS = 178, enumerator in enum:sparx5_target
6427 #define QSYS_PAUSE_CFG(r) __REG(TARGET_QSYS,\
6455 #define QSYS_ATOP(r) __REG(TARGET_QSYS,\
6465 #define QSYS_FWD_PRESSURE(r) __REG(TARGET_QSYS,\
6481 #define QSYS_ATOP_TOT_CFG __REG(TARGET_QSYS,\
6491 #define QSYS_CAL_AUTO(r) __REG(TARGET_QSYS,\
6501 #define QSYS_CAL_CTRL __REG(TARGET_QSYS,\
6523 #define QSYS_RAM_INIT __REG(TARGET_QSYS,\
H A Dsparx5_main.c198 { TARGET_QSYS, 0x110a0000, 2 }, /* 0x6110a0000 */

Completed in 221 milliseconds