Searched refs:IMX7ULP_CLK_SPLL_BUS_CLK (Results 1 - 3 of 3) sorted by relevance

/linux-master/include/dt-bindings/clock/
H A Dimx7ulp-clock.h57 #define IMX7ULP_CLK_SPLL_BUS_CLK 43 macro
/linux-master/scripts/dtc/include-prefixes/dt-bindings/clock/
H A Dimx7ulp-clock.h57 #define IMX7ULP_CLK_SPLL_BUS_CLK 43 macro
/linux-master/drivers/clk/imx/
H A Dclk-imx7ulp.c102 hws[IMX7ULP_CLK_SPLL_BUS_CLK] = imx_clk_hw_divider_gate("spll_bus_clk", "spll_sel", CLK_SET_RATE_GATE, base + 0x604, 8, 3, 0, ulp_div_table, &imx_ccm_lock);

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