Searched refs:IMX6SL_CLK_PLL5_VIDEO_DIV (Results 1 - 3 of 3) sorted by relevance

/linux-master/include/dt-bindings/clock/
H A Dimx6sl-clock.h25 #define IMX6SL_CLK_PLL5_VIDEO_DIV 16 macro
/linux-master/scripts/dtc/include-prefixes/dt-bindings/clock/
H A Dimx6sl-clock.h25 #define IMX6SL_CLK_PLL5_VIDEO_DIV 16 macro
/linux-master/drivers/clk/imx/
H A Dclk-imx6sl.c270 hws[IMX6SL_CLK_PLL5_VIDEO_DIV] = clk_hw_register_divider_table(NULL, "pll5_video_div", "pll5_post_div", CLK_SET_RATE_PARENT, base + 0x170, 30, 2, 0, video_div_table, &imx_ccm_lock);
438 hws[IMX6SL_CLK_PLL5_VIDEO_DIV]->clk);

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