Searched refs:IMX6SLL_CLK_PLL5_POST_DIV (Results 1 - 3 of 3) sorted by relevance

/linux-master/scripts/dtc/include-prefixes/dt-bindings/clock/
H A Dimx6sll-clock.h56 #define IMX6SLL_CLK_PLL5_POST_DIV 45 macro
/linux-master/include/dt-bindings/clock/
H A Dimx6sll-clock.h56 #define IMX6SLL_CLK_PLL5_POST_DIV 45 macro
/linux-master/drivers/clk/imx/
H A Dclk-imx6sll.c179 hws[IMX6SLL_CLK_PLL5_POST_DIV] = clk_hw_register_divider_table(NULL, "pll5_post_div", "pll5_video",

Completed in 202 milliseconds