Searched refs:IMX6QDL_CLK_PLL5_VIDEO_DIV (Results 1 - 3 of 3) sorted by relevance
| /linux-master/scripts/dtc/include-prefixes/dt-bindings/clock/ |
| H A D | imx6qdl-clock.h | 205 #define IMX6QDL_CLK_PLL5_VIDEO_DIV 195 macro
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| /linux-master/include/dt-bindings/clock/ |
| H A D | imx6qdl-clock.h | 205 #define IMX6QDL_CLK_PLL5_VIDEO_DIV 195 macro
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| /linux-master/drivers/clk/imx/ |
| H A D | clk-imx6q.c | 151 case IMX6QDL_CLK_PLL5_VIDEO_DIV:
604 hws[IMX6QDL_CLK_PLL5_VIDEO_DIV] = clk_hw_register_divider_table(NULL, "pll5_video_div", "pll5_post_div", CLK_SET_RATE_PARENT, base + 0x170, 30, 2, 0, video_div_table, &imx_ccm_lock);
932 clk_set_parent(hws[IMX6QDL_CLK_IPU1_DI0_PRE_SEL]->clk, hws[IMX6QDL_CLK_PLL5_VIDEO_DIV]->clk);
933 clk_set_parent(hws[IMX6QDL_CLK_IPU1_DI1_PRE_SEL]->clk, hws[IMX6QDL_CLK_PLL5_VIDEO_DIV]->clk);
934 clk_set_parent(hws[IMX6QDL_CLK_IPU2_DI0_PRE_SEL]->clk, hws[IMX6QDL_CLK_PLL5_VIDEO_DIV]->clk);
935 clk_set_parent(hws[IMX6QDL_CLK_IPU2_DI1_PRE_SEL]->clk, hws[IMX6QDL_CLK_PLL5_VIDEO_DIV]->clk);
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Completed in 89 milliseconds