Searched refs:CSR9 (Results 1 - 11 of 11) sorted by relevance

/linux-master/drivers/net/ethernet/dec/tulip/
H A Dxircom_cb.c57 #define CSR9 0x48 macro
96 CSR0, CSR6, CSR7, CSR9, CSR10, CSR15
1005 xw32(CSR9, 1 << 12); /* enable boot rom access */
1010 tuple = xr32(CSR9);
1012 link = xr32(CSR9);
1014 data_id = xr32(CSR9);
1016 data_count = xr32(CSR9);
1023 addr[j] = xr32(CSR9) & 0xff;
H A Dmedia.c54 void __iomem *mdio_addr = ioaddr + CSR9;
115 void __iomem *mdio_addr = ioaddr + CSR9;
H A Deeprom.c345 void __iomem *ee_addr = tp->base_addr + CSR9;
H A Dtulip.h115 CSR9 = 0x48, enumerator in enum:tulip_offsets
H A Dtulip_core.c1508 value = ioread32(ioaddr + CSR9);
/linux-master/drivers/net/ethernet/amd/
H A Dariadne.h69 #define CSR9 0x0900 /* - Logical Address Filter, LADRF[31:16] */ macro
H A Dariadne.c435 lance->RAP = CSR9; /* Logical Address Filter, LADRF[31:16] */
/linux-master/drivers/net/wireless/ralink/rt2x00/
H A Drt2400pci.h146 * CSR9: Maximum frame length register.
149 #define CSR9 0x0024 macro
H A Drt2500pci.h210 * CSR9: Maximum frame length register.
213 #define CSR9 0x0024 macro
H A Drt2400pci.c825 reg = rt2x00mmio_register_read(rt2x00dev, CSR9);
828 rt2x00mmio_register_write(rt2x00dev, CSR9, reg);
H A Drt2500pci.c910 reg = rt2x00mmio_register_read(rt2x00dev, CSR9);
913 rt2x00mmio_register_write(rt2x00dev, CSR9, reg);

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