Searched refs:CSR7 (Results 1 - 9 of 9) sorted by relevance

/linux-master/drivers/net/ethernet/dec/tulip/
H A Dpnic.c62 iowrite32((ioread32(ioaddr + CSR7) & ~TPLnkFail) | TPLnkPass, ioaddr + CSR7);
83 iowrite32((ioread32(ioaddr + CSR7) & ~TPLnkPass) | TPLnkFail, ioaddr + CSR7);
94 if(!ioread32(ioaddr + CSR7)) {
162 if(!ioread32(ioaddr + CSR7)) {
168 iowrite32(tulip_tbl[tp->chip_id].valid_intrs, ioaddr + CSR7);
H A Dinterrupt.c327 iowrite32(tulip_tbl[tp->chip_id].valid_intrs, tp->base_addr+CSR7);
561 iowrite32(tulip_tbl[tp->chip_id].valid_intrs&~RxPollInt, ioaddr + CSR7);
735 iowrite32(tulip_tbl[tp->chip_id].valid_intrs, ioaddr + CSR7);
752 iowrite32(0x00, ioaddr + CSR7);
757 iowrite32(((~csr5) & 0x0001ebef) | AbnormalIntr | TimerInt, ioaddr + CSR7);
795 iowrite32(0x00, ioaddr + CSR7);
804 ioaddr + CSR7);
H A Dxircom_cb.c55 #define CSR7 0x38 macro
96 CSR0, CSR6, CSR7, CSR9, CSR10, CSR15
871 val = xr32(CSR7); /* Interrupt enable register */
873 xw32(CSR7, val);
887 val = xr32(CSR7); /* Interrupt enable register */
889 xw32(CSR7, val);
902 val = xr32(CSR7); /* Interrupt enable register */
904 xw32(CSR7, val);
918 xw32(CSR7, 0);
931 val = xr32(CSR7); /* Interrup
[all...]
H A Dtulip.h44 int valid_intrs; /* CSR7 interrupt enable settings */
113 CSR7 = 0x38, enumerator in enum:tulip_offsets
H A Dtulip_core.c435 iowrite32(ioread32(ioaddr+CSR7)| 0x00008010, ioaddr + CSR7); local
481 iowrite32(tulip_tbl[tp->chip_id].valid_intrs, ioaddr + CSR7);
555 (int)ioread32(ioaddr + CSR7),
757 iowrite32 (0x00000000, ioaddr + CSR7);
/linux-master/drivers/net/wireless/ralink/rt2x00/
H A Drt2400pci.c969 reg = rt2x00mmio_register_read(rt2x00dev, CSR7);
970 rt2x00mmio_register_write(rt2x00dev, CSR7, reg);
1378 reg = rt2x00mmio_register_read(rt2x00dev, CSR7);
1379 rt2x00mmio_register_write(rt2x00dev, CSR7, reg);
H A Drt2400pci.h106 * CSR7: Interrupt source register.
116 #define CSR7 0x001c macro
H A Drt2500pci.h117 * CSR7: Interrupt source register.
141 #define CSR7 0x001c macro
H A Drt2500pci.c1123 reg = rt2x00mmio_register_read(rt2x00dev, CSR7);
1124 rt2x00mmio_register_write(rt2x00dev, CSR7, reg);
1506 reg = rt2x00mmio_register_read(rt2x00dev, CSR7);
1507 rt2x00mmio_register_write(rt2x00dev, CSR7, reg);

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