Searched refs:CSR5 (Results 1 - 12 of 12) sorted by relevance

/linux-master/drivers/net/ethernet/dec/tulip/
H A Dinterrupt.c93 if(((ioread32(tp->base_addr + CSR5)>>17)&0x07) == 4) {
135 if (ioread32(tp->base_addr + CSR5) == 0xffffffff) {
140 iowrite32((RxIntr | RxNoBuf), tp->base_addr + CSR5);
280 } while ((ioread32(tp->base_addr + CSR5) & RxIntr));
544 csr5 = ioread32(ioaddr + CSR5);
571 iowrite32(csr5 & 0x0001ff3f, ioaddr + CSR5);
575 iowrite32(csr5 & 0x0001ffff, ioaddr + CSR5);
587 csr5, ioread32(ioaddr + CSR5));
667 "The transmitter stopped. CSR5 is %x, CSR6 %x, new CSR6 %x\n",
726 iowrite32(0x0800f7ba, ioaddr + CSR5);
[all...]
H A Dpnic.c59 netdev_dbg(dev, "PNIC link changed state %08x, CSR5 %08x\n",
61 if (ioread32(ioaddr + CSR5) & TPLnkFail) {
75 } else if (ioread32(ioaddr + CSR5) & TPLnkPass) {
112 int csr5 = ioread32(ioaddr + CSR5);
115 netdev_dbg(dev, "PNIC timer PHY status %08x, %s CSR5 %08x\n",
126 netdev_dbg(dev, "%s link beat failed, CSR12 %04x, CSR5 %08x, PHY %03x\n",
129 ioread32(ioaddr + CSR5),
H A Dtulip.h111 CSR5 = 0x28, enumerator in enum:tulip_offsets
138 /* The bits in the CSR5 status registers, mostly interrupt sources. */
158 /* bit mask for CSR5 TX/RX process state */
542 while (--i && (ioread32(ioaddr + CSR5) & (CSR5_TS|CSR5_RS)))
546 netdev_dbg(tp->dev, "tulip_stop_rxtx() failed (CSR5 0x%x CSR6 0x%x)\n",
547 ioread32(ioaddr + CSR5),
H A Dxircom_cb.c53 #define CSR5 0x28 macro
333 status = xr32(CSR5);
363 xw32(CSR5, status);
645 val = xr32(CSR5); /* Status register */
652 xw32(CSR5, val);
666 if (!(xr32(CSR5) & (7 << 20))) /* transmitter disabled */
680 if (!(xr32(CSR5) & (7 << 17))) /* receiver disabled */
H A Dtimer.c30 ioread32(ioaddr + CSR5), ioread32(ioaddr + CSR6),
H A Dtulip_core.c434 iowrite32(ioread32(ioaddr+CSR5)| 0x00008010, ioaddr + CSR5); local
442 } else if (ioread32(ioaddr + CSR5) & TPLnkPass)
480 iowrite32(tulip_tbl[tp->chip_id].valid_intrs, ioaddr + CSR5);
486 netdev_dbg(dev, "Done tulip_up(), CSR0 %08x, CSR5 %08x CSR6 %08x\n",
488 ioread32(ioaddr + CSR5),
544 ioread32(ioaddr + CSR5), ioread32(ioaddr + CSR12),
553 (int)ioread32(ioaddr + CSR5),
560 ioread32(ioaddr + CSR5), ioread32(ioaddr + CSR12));
830 ioread32 (ioaddr + CSR5));
[all...]
H A D21142.c151 "21143 link status interrupt %08x, CSR5 %x, %08x\n",
206 netdev_dbg(dev, " Restarting Tx and Rx, CSR5 is %08x\n",
207 ioread32(ioaddr + CSR5));
/linux-master/drivers/net/wireless/ralink/rt2x00/
H A Drt2400pci.h90 * CSR5: BSSID register 0.
92 #define CSR5 0x0014 macro
H A Drt2500pci.h101 * CSR5: BSSID register 0.
103 #define CSR5 0x0014 macro
H A Drt2400pci.c307 rt2x00mmio_register_multiwrite(rt2x00dev, CSR5,
H A Drt2500pci.c313 rt2x00mmio_register_multiwrite(rt2x00dev, CSR5,
/linux-master/drivers/net/ethernet/amd/
H A Dpcnet32.c204 #define CSR5 5 macro
688 /* set SUSPEND (SPND) - CSR5 bit 0 */
689 csr5 = a->read_csr(ioaddr, CSR5);
690 a->write_csr(ioaddr, CSR5, csr5 | CSR5_SUSPEND);
694 while (!(a->read_csr(ioaddr, CSR5) & CSR5_SUSPEND)) {
713 int csr5 = lp->a->read_csr(ioaddr, CSR5);
714 /* clear SUSPEND (SPND) - CSR5 bit 0 */
715 lp->a->write_csr(ioaddr, CSR5, csr5 & ~CSR5_SUSPEND);

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