Searched refs:CSR2 (Results 1 - 13 of 13) sorted by relevance
| /linux-master/drivers/media/pci/dt3155/ |
| H A D | dt3155.h | 48 #define CSR2 0x10 macro
105 /* CSR2 bit masks */
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| H A D | dt3155.c | 170 write_i2c_reg(pd->regs, CSR2, pd->csr2 | BUSY_EVEN | BUSY_ODD);
181 write_i2c_reg_nowait(pd->regs, CSR2, pd->csr2);
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| /linux-master/drivers/net/ethernet/amd/ |
| H A D | ariadne.h | 64 #define CSR2 0x0200 /* - IADR[23:16] */ macro
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| H A D | sun3lance.c | 205 #define CSR2 2 /* init block addr (high) */ macro
498 REGA(CSR2) = dvma_vtob(&(MEM->init)) >> 16;
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| H A D | atarilance.c | 305 #define CSR2 2 /* init block addr (high) */ macro
652 REGA( CSR2 ) = 0;
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| /linux-master/drivers/net/ethernet/dec/tulip/ |
| H A D | tulip.h | 108 CSR2 = 0x10, enumerator in enum:tulip_offsets
352 0x02000000 means use the ring start address in CSR2/3.
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| H A D | xircom_cb.c | 50 #define CSR2 0x10 macro
545 This is accomplished by writing to the CSR2 port. The documentation
553 xw32(CSR2, 0);
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| H A D | interrupt.c | 97 iowrite32(0x01, tp->base_addr + CSR2);
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| H A D | tulip_core.c | 483 iowrite32(0, ioaddr + CSR2); /* Rx poll demand */
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| /linux-master/drivers/net/wireless/ralink/rt2x00/ |
| H A D | rt2400pci.h | 69 * CSR2: System admin status register (invalid).
71 #define CSR2 0x0008 macro
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| H A D | rt2500pci.h | 80 * CSR2: System admin status register (invalid).
82 #define CSR2 0x0008 macro
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| /linux-master/drivers/net/ethernet/renesas/ |
| H A D | ravb.h | 212 CSR2 = 0x0808, enumerator in enum:ravb_reg
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| H A D | ravb_main.c | 486 CSR2);
2489 ret = ravb_endisable_csum_gbeth(ndev, CSR2, val, CSR0_RPE);
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