| /linux-master/drivers/net/ethernet/dec/tulip/ |
| H A D | media.c | 205 iowrite32(get_u16(rst + 1 + (i<<1)) << 16, ioaddr + CSR15); local
218 iowrite32(csr15dir, ioaddr + CSR15); /* Direction */
219 iowrite32(csr15val, ioaddr + CSR15); /* Data */
232 iowrite32(csr15dir, ioaddr + CSR15); /* Direction */
233 iowrite32(csr15val, ioaddr + CSR15); /* Data */
237 netdev_dbg(dev, "Setting CSR15 to %08x/%08x\n",
260 iowrite32(get_u16(&reset_sequence[i]) << 16, ioaddr + CSR15); local
263 ioread32(ioaddr + CSR15);
275 iowrite32(get_u16(&init_sequence[i]) << 16, ioaddr + CSR15); local
277 ioread32(ioaddr + CSR15); /* flus
330 iowrite32(get_u16(rst + 1 + (i<<1)) << 16, ioaddr + CSR15); local
[all...] |
| H A D | 21142.c | 81 iowrite16(t21142_csr15[dev->if_port], ioaddr + CSR15);
89 iowrite16(8, ioaddr + CSR15);
130 iowrite32(tp->mtable->csr15dir, ioaddr + CSR15);
131 iowrite32(tp->mtable->csr15val, ioaddr + CSR15);
133 iowrite16(0x0008, ioaddr + CSR15);
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| H A D | timer.c | 32 ioread32(ioaddr + CSR14), ioread32(ioaddr + CSR15));
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| H A D | xircom_cb.c | 63 #define CSR15 0x78 macro
96 CSR0, CSR6, CSR7, CSR9, CSR10, CSR15
1053 xw32(CSR15, 0x0008);
1055 xw32(CSR15, 0xa8050000);
1057 xw32(CSR15, 0xa00f0000);
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| H A D | tulip.h | 121 CSR15 = 0x78, enumerator in enum:tulip_offsets
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| H A D | tulip_core.c | 412 iowrite32(0x0008, ioaddr + CSR15);
441 iowrite32(0x0001, ioaddr + CSR15);
546 ioread32(ioaddr + CSR15));
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| H A D | de2104x.c | 152 CSR15 = 0x78, enumerator in enum:__anon740
927 dw32(CSR15, de->media[media].csr15);
943 dr32(CSR13), dr32(CSR14), dr32(CSR15));
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| /linux-master/drivers/net/ethernet/amd/ |
| H A D | ariadne.h | 75 #define CSR15 0x0f00 /* - Mode Register */ macro
236 * Bit definitions for CSR15 (Mode Register)
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| H A D | sun3lance.c | 208 #define CSR15 15 /* promiscuous mode */ macro
896 REGA( CSR15 ) = 0x8000; /* Set promiscuous mode */
907 REGA( CSR15 ) = 0; /* Unset promiscuous mode */
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| H A D | ariadne.c | 451 lance->RAP = CSR15; /* Mode Register */
658 lance->RAP = CSR15; /* Mode Register */
674 lance->RAP = CSR15; /* Mode Register */
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| H A D | atarilance.c | 308 #define CSR15 15 /* promiscuous mode */ macro
1086 REGA( CSR15 ) = 0x8000; /* Set promiscuous mode */
1097 REGA( CSR15 ) = 0; /* Unset promiscuous mode */
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| H A D | pcnet32.c | 206 #define CSR15 15 macro
773 csr15 = lp->a->read_csr(ioaddr, CSR15) & ~0x0180;
776 lp->a->write_csr(ioaddr, CSR15, csr15);
1052 /* set int loopback in CSR15 */
1053 x = a->read_csr(ioaddr, CSR15) & 0xfffc;
1054 lp->a->write_csr(ioaddr, CSR15, x | 0x0044);
1111 x = a->read_csr(ioaddr, CSR15);
1112 a->write_csr(ioaddr, CSR15, (x & ~0x0044)); /* reset bits 6 and 2 */
2722 csr15 = lp->a->read_csr(ioaddr, CSR15);
2729 lp->a->write_csr(ioaddr, CSR15, csr1
[all...] |
| /linux-master/drivers/net/wireless/ralink/rt2x00/ |
| H A D | rt2400pci.h | 209 * CSR15: Synchronization status register.
214 #define CSR15 0x003c macro
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| H A D | rt2500pci.h | 286 * CSR15: Synchronization status register.
291 #define CSR15 0x003c macro
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| H A D | rt2400pci.c | 1703 reg = rt2x00mmio_register_read(rt2x00dev, CSR15);
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| H A D | rt2500pci.c | 2001 reg = rt2x00mmio_register_read(rt2x00dev, CSR15);
|