Searched refs:CLK_TOP_MSDC30_3_SEL (Results 1 - 15 of 15) sorted by relevance
| /linux-master/scripts/dtc/include-prefixes/dt-bindings/clock/ |
| H A D | mt8135-clk.h | 83 #define CLK_TOP_MSDC30_3_SEL 72 macro
|
| H A D | mt8173-clk.h | 109 #define CLK_TOP_MSDC30_3_SEL 99 macro
|
| H A D | mediatek,mt6795-clk.h | 107 #define CLK_TOP_MSDC30_3_SEL 96 macro
|
| H A D | mt2701-clk.h | 126 #define CLK_TOP_MSDC30_3_SEL 115 macro
|
| H A D | mt2712-clk.h | 146 #define CLK_TOP_MSDC30_3_SEL 115 macro
|
| /linux-master/include/dt-bindings/clock/ |
| H A D | mt8135-clk.h | 83 #define CLK_TOP_MSDC30_3_SEL 72 macro
|
| H A D | mt8173-clk.h | 109 #define CLK_TOP_MSDC30_3_SEL 99 macro
|
| H A D | mediatek,mt6795-clk.h | 107 #define CLK_TOP_MSDC30_3_SEL 96 macro
|
| H A D | mt2701-clk.h | 126 #define CLK_TOP_MSDC30_3_SEL 115 macro
|
| H A D | mt2712-clk.h | 146 #define CLK_TOP_MSDC30_3_SEL 115 macro
|
| /linux-master/drivers/clk/mediatek/ |
| H A D | clk-mt6795-topckgen.c | 477 TOP_MUX_GATE(CLK_TOP_MSDC30_3_SEL, "msdc30_3_sel", msdc30_3_parents, 0x80, 8, 3, 15, 0),
|
| H A D | clk-mt8173-topckgen.c | 559 MUX_GATE_FLAGS(CLK_TOP_MSDC30_3_SEL, "msdc30_3_sel", msdc30_3_parents,
|
| H A D | clk-mt8135.c | 368 MUX_GATE(CLK_TOP_MSDC30_3_SEL, "msdc30_3_sel", msdc30_parents, 0x0148, 16, 3, 23),
|
| H A D | clk-mt2712.c | 670 MUX_GATE(CLK_TOP_MSDC30_3_SEL, "msdc30_3_sel", msdc30_3_parents,
|
| H A D | clk-mt2701.c | 573 MUX_GATE(CLK_TOP_MSDC30_3_SEL, "msdc30_3_sel", msdc30_parents,
|
Completed in 287 milliseconds