Searched refs:CLK_TOP_I2SI1_SEL (Results 1 - 3 of 3) sorted by relevance

/linux-master/scripts/dtc/include-prefixes/dt-bindings/clock/
H A Dmt2712-clk.h182 #define CLK_TOP_I2SI1_SEL 151 macro
/linux-master/include/dt-bindings/clock/
H A Dmt2712-clk.h182 #define CLK_TOP_I2SI1_SEL 151 macro
/linux-master/drivers/clk/mediatek/
H A Dclk-mt2712.c727 MUX_GATE(CLK_TOP_I2SI1_SEL, "i2si1_sel", i2so1_parents, 0x530, 8, 2, 15),

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