Searched refs:CLK_TOP_HDCP_SEL (Results 1 - 6 of 6) sorted by relevance
| /linux-master/scripts/dtc/include-prefixes/dt-bindings/clock/ |
| H A D | mt8173-clk.h | 128 #define CLK_TOP_HDCP_SEL 118 macro
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| H A D | mt2712-clk.h | 166 #define CLK_TOP_HDCP_SEL 135 macro
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| /linux-master/include/dt-bindings/clock/ |
| H A D | mt8173-clk.h | 128 #define CLK_TOP_HDCP_SEL 118 macro
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| H A D | mt2712-clk.h | 166 #define CLK_TOP_HDCP_SEL 135 macro
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| /linux-master/drivers/clk/mediatek/ |
| H A D | clk-mt8173-topckgen.c | 600 MUX_GATE(CLK_TOP_HDCP_SEL, "hdcp_sel", hdcp_parents, 0x00d0, 8, 2, 15),
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| H A D | clk-mt2712.c | 704 MUX_GATE(CLK_TOP_HDCP_SEL, "hdcp_sel", hdcp_parents, 0x0d0, 8, 2, 15),
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