Searched refs:CLK_TOP_DPILVDS_SEL (Results 1 - 9 of 9) sorted by relevance
| /linux-master/scripts/dtc/include-prefixes/dt-bindings/clock/ |
| H A D | mt8135-clk.h | 95 #define CLK_TOP_DPILVDS_SEL 84 macro
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| H A D | mt8173-clk.h | 126 #define CLK_TOP_DPILVDS_SEL 116 macro
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| H A D | mt2712-clk.h | 164 #define CLK_TOP_DPILVDS_SEL 133 macro
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| /linux-master/include/dt-bindings/clock/ |
| H A D | mt8135-clk.h | 95 #define CLK_TOP_DPILVDS_SEL 84 macro
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| H A D | mt8173-clk.h | 126 #define CLK_TOP_DPILVDS_SEL 116 macro
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| H A D | mt2712-clk.h | 164 #define CLK_TOP_DPILVDS_SEL 133 macro
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| /linux-master/drivers/clk/mediatek/ |
| H A D | clk-mt8173-topckgen.c | 595 MUX_GATE(CLK_TOP_DPILVDS_SEL, "dpilvds_sel", dpilvds_parents,
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| H A D | clk-mt8135.c | 385 MUX_GATE(CLK_TOP_DPILVDS_SEL, "dpilvds_sel", dpilvds_parents, 0x015c, 24, 3, 31),
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| H A D | clk-mt2712.c | 700 MUX_GATE(CLK_TOP_DPILVDS_SEL, "dpilvds_sel", dpilvds_parents, 0x0c0, 24, 3, 31),
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Completed in 254 milliseconds