Searched refs:CLK_TOP_APLL_DIV_PDN2 (Results 1 - 3 of 3) sorted by relevance

/linux-master/scripts/dtc/include-prefixes/dt-bindings/clock/
H A Dmt2712-clk.h211 #define CLK_TOP_APLL_DIV_PDN2 180 macro
/linux-master/include/dt-bindings/clock/
H A Dmt2712-clk.h211 #define CLK_TOP_APLL_DIV_PDN2 180 macro
/linux-master/drivers/clk/mediatek/
H A Dclk-mt2712.c825 GATE_TOP0(CLK_TOP_APLL_DIV_PDN2, "apll_div_pdn2", "i2so3_sel", 2),

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