| /linux-master/scripts/dtc/include-prefixes/dt-bindings/clock/ |
| H A D | mt8135-clk.h | 114 #define CLK_APMIXED_TVDPLL 7 macro
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| H A D | mt8167-clk.h | 17 #define CLK_APMIXED_TVDPLL (CLK_APMIXED_NR_CLK + 0) macro
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| H A D | mt6797-clk.h | 113 #define CLK_APMIXED_TVDPLL 6 macro
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| H A D | mt8173-clk.h | 163 #define CLK_APMIXED_TVDPLL 8 macro
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| H A D | mediatek,mt6795-clk.h | 147 #define CLK_APMIXED_TVDPLL 6 macro
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| H A D | mt2701-clk.h | 180 #define CLK_APMIXED_TVDPLL 6 macro
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| H A D | mt2712-clk.h | 22 #define CLK_APMIXED_TVDPLL 10 macro
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| H A D | mt6779-clk.h | 176 #define CLK_APMIXED_TVDPLL 11 macro
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| H A D | mt8183-clk.h | 19 #define CLK_APMIXED_TVDPLL 8 macro
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| H A D | mt8192-clk.h | 308 #define CLK_APMIXED_TVDPLL 7 macro
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| /linux-master/include/dt-bindings/clock/ |
| H A D | mt8135-clk.h | 114 #define CLK_APMIXED_TVDPLL 7 macro
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| H A D | mt8167-clk.h | 17 #define CLK_APMIXED_TVDPLL (CLK_APMIXED_NR_CLK + 0) macro
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| H A D | mt6797-clk.h | 113 #define CLK_APMIXED_TVDPLL 6 macro
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| H A D | mt8173-clk.h | 163 #define CLK_APMIXED_TVDPLL 8 macro
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| H A D | mediatek,mt6795-clk.h | 147 #define CLK_APMIXED_TVDPLL 6 macro
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| H A D | mt2701-clk.h | 180 #define CLK_APMIXED_TVDPLL 6 macro
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| H A D | mt2712-clk.h | 22 #define CLK_APMIXED_TVDPLL 10 macro
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| H A D | mt6779-clk.h | 176 #define CLK_APMIXED_TVDPLL 11 macro
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| H A D | mt8183-clk.h | 19 #define CLK_APMIXED_TVDPLL 8 macro
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| /linux-master/drivers/clk/mediatek/ |
| H A D | clk-mt8192-apmixedsys.c | 87 PLL_B(CLK_APMIXED_TVDPLL, "tvdpll", 0x0380, 0x038c, 0x00000000,
143 FH(CLK_APMIXED_TVDPLL, FH_TVDPLL, 0x154),
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| H A D | clk-mt8186-apmixedsys.c | 73 PLL(CLK_APMIXED_TVDPLL, "tvdpll", 0x0264, 0x0270, 0,
127 FH(CLK_APMIXED_TVDPLL, FH_TVDPLL, 0x00A0),
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| H A D | clk-mt6795-apmixedsys.c | 56 PLL(CLK_APMIXED_TVDPLL, "tvdpll", 0x270, 0x27c, 0, 0, 21, 0x270, 4, 0x0, 0x274, 0),
109 FH(CLK_APMIXED_TVDPLL, FH_TVDPLL, 0xc4),
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| H A D | clk-mt8173-apmixedsys.c | 73 PLL(CLK_APMIXED_TVDPLL, "tvdpll", 0x270, 0x27c, 0, 0, 21, 0x270, 4, 0x0, 0x274, 0),
128 FH(CLK_APMIXED_TVDPLL, FH_TVDPLL, 0xc4),
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| H A D | clk-mt8167-apmixedsys.c | 71 PLL(CLK_APMIXED_TVDPLL, "tvdpll", 0x01C0, 0x01D0, 0, 0,
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| H A D | clk-mt8135-apmixedsys.c | 44 PLL(CLK_APMIXED_TVDPLL, "tvdpll", 0x294, 0x2ac, 0x80000000, 0, 31, 0x294, 6, 0x0, 0x298, 0),
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