Searched refs:registers (Results 1 - 25 of 54) sorted by relevance

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/haiku-fatelf/src/add-ons/kernel/drivers/graphics/radeon_hd/
H A Dradeon_hd.cpp250 uint32 bus_cntl = read32(info.registers + R600_BUS_CNTL);
251 uint32 d1vga_control = read32(info.registers + AVIVO_D1VGA_CONTROL);
252 uint32 d2vga_control = read32(info.registers + AVIVO_D2VGA_CONTROL);
254 = read32(info.registers + AVIVO_VGA_RENDER_CONTROL);
255 uint32 rom_cntl = read32(info.registers + R600_ROM_CNTL);
258 write32(info.registers + R600_BUS_CNTL, (bus_cntl & ~R600_BIOS_ROM_DIS));
260 write32(info.registers + AVIVO_D1VGA_CONTROL, (d1vga_control
263 write32(info.registers + AVIVO_D2VGA_CONTROL, (d2vga_control
266 write32(info.registers + AVIVO_VGA_RENDER_CONTROL,
269 write32(info.registers
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H A Dsensors.cpp30 rawTemp = (read32(info.registers + SI_CG_MULT_THERMAL_STATUS)
40 uint32 offset = (read32(info.registers + EVERGREEN_CG_THERMAL_CTRL)
42 rawTemp = (read32(info.registers + EVERGREEN_CG_TS0_STATUS)
53 uint32 rawTemp = read32(info.registers + EVERGREEN_CG_THERMAL_STATUS)
59 rawTemp = (read32(info.registers + EVERGREEN_CG_MULT_THERMAL_STATUS)
74 rawTemp = (read32(info.registers + R700_CG_MULT_THERMAL_STATUS)
88 rawTemp = (read32(info.registers + R600_CG_THERMAL_STATUS)
H A Dradeon_hd_private.h37 uint8* registers; member in struct:radeon_info
H A Ddevice.cpp84 uint32 oldValue = read32(info.registers + reg);
89 write32(info.registers + reg, value);
91 value = read32(info.registers + reg);
/haiku-fatelf/src/bin/gdb/gdb/gdbserver/
H A Dregcache.c35 char *registers; member in struct:inferior_regcache_data
55 /* FIXME - fetch registers for INF */
105 in case there are registers the target never fetches. This way they'll
107 regcache->registers = calloc (1, register_bytes);
108 if (regcache->registers == NULL)
122 free (regcache->registers);
147 char *registers = get_regcache (current_inferior, 1)->registers; local
149 convert_int_to_ascii (registers, buf, register_bytes);
156 char *registers local
206 char *registers = get_regcache (current_inferior, fetch)->registers; local
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/haiku-fatelf/src/bin/gdb/gdb/
H A Dsparc-stub.c49 * g return the value of the CPU registers hex data or ENN
50 * G set the value of the CPU registers OK or ENN
108 /* Number of bytes of registers. */
182 std %l0, [%sp + 0 * 4] ! save L & I registers
209 ! + registers[72] local var
211 std %g0, [%sp + (24 + 0) * 4] ! registers[Gx]
216 std %i0, [%sp + (24 + 8) * 4] ! registers[Ox]
236 add %sp, 24 * 4, %o0 ! Pass address of registers
238 ! Reload all of the registers that aren't on the stack
240 ld [%sp + (24 + 1) * 4], %g1 ! registers[G
555 handle_exception(unsigned long *registers) argument
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H A Dm32r-stub.c57 * g return the value of the CPU registers hex data or ENN
58 * G set the value of the CPU registers OK or ENN
118 /* Number of bytes of registers. */
153 static int registers[NUMREGS]; variable
226 mem2hex ((unsigned char *) &registers[PC], buf, 4, 0);
242 ptr = mem2hex ((unsigned char *) &registers[PC], ptr, 4, 0); /* PC */
248 ptr = mem2hex ((unsigned char *) &registers[R13], ptr, 4, 0); /* FP */
254 ptr = mem2hex ((unsigned char *) &registers[R15], ptr, 4, 0); /* SP */
260 mem2hex ((unsigned char *) &registers[PC], buf, 4, 0);
261 switch (registers[R
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H A Di386-stub.c57 * g return the value of the CPU registers hex data or ENN
58 * G set the value of the CPU registers OK or ENN
116 /* Number of registers. */
119 /* Number of bytes of registers. */
130 int registers[NUMREGS]; variable
142 /* Restore the program's registers (including the stack pointer, which
179 /* GDB stores segment registers in 32-bit words (that's just the way
180 m-i386v.h is written). So zero the appropriate areas in registers. */
221 /* OK to clobber temp registers; we're just going to end up in set_mem_err. */
580 that the compiler won't save any registers (i
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H A Dm68k-stub.c73 * g return the value of the CPU registers hex data or ENN
74 * G set the value of the CPU registers OK or ENN
143 /* there are 180 bytes of registers on a 68020 w/68881 */
144 /* many of the fpa registers are 12 byte (96 bit) registers */
159 fsave data part of the registers which GDB deals with like any
160 other registers. This should not be a performance problem if the
161 ability to read individual registers is added to the protocol. */
183 int registers[NUMREGBYTES/4];
325 moveml d0-d7/a0-a6,_registers /* save registers */
182 int registers[NUMREGBYTES/4]; variable
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H A Dsh-stub.c55 read registers g
185 * Number of bytes for registers
276 int registers[NUMREGBYTES / 4]; variable
561 instrMem = (short *) registers[PC];
568 if (registers[SR] & T_BIT_MASK)
577 instrMem = (short *) (registers[PC] + displacement + 4);
584 if (registers[SR] & T_BIT_MASK)
595 instrMem = (short *) (registers[PC] + displacement + 4);
608 instrMem = (short *) (registers[PC] + displacement + 4);
614 instrMem = (short *) registers[re
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/haiku-fatelf/src/add-ons/kernel/drivers/graphics/intel_extreme/
H A Ddriver.h46 return *(volatile uint16*)(info.registers
55 return *(volatile uint32*)(info.registers
64 *(volatile uint16*)(info.registers
73 *(volatile uint32*)(info.registers
H A Dintel_extreme_private.h28 uint8* registers; member in struct:intel_info
47 panic("find_reg is only supposed to be used for unrouped registers\n");
H A Dintel_extreme.cpp37 init_overlay_registers(overlay_registers* registers) argument
39 memset(registers, 0, B_PAGE_SIZE);
41 registers->contrast_correction = 0x48;
42 registers->saturation_cos_correction = 0x9a;
237 // TODO: registers are mapped twice (by us and intel_gart), maybe we
245 (void**)&info.registers);
341 // setup overlay registers
/haiku-fatelf/src/add-ons/accelerants/intel_extreme/
H A Doverlay.cpp195 overlay_registers* registers = gInfo->overlay_registers; local
197 registers->color_key_red = red;
198 registers->color_key_green = green;
199 registers->color_key_blue = blue;
200 registers->color_key_mask_red = ~redMask;
201 registers->color_key_mask_green = ~greenMask;
202 registers->color_key_mask_blue = ~blueMask;
203 registers->color_key_enabled = true;
287 overlay_registers* registers = gInfo->overlay_registers;
290 registers
555 overlay_registers* registers = gInfo->overlay_registers; local
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H A Daccelerant.h34 uint8* registers; member in struct:accelerant_info
79 return *(volatile uint32*)(gInfo->registers
87 *(volatile uint32*)(gInfo->registers
H A Dengine.cpp101 uint32 registers; local
102 // G33 does not need a physical address for the overlay registers
104 registers = gInfo->shared_info->physical_overlay_registers;
106 registers = gInfo->shared_info->overlay_offset;
108 Write(registers | (updateCoefficients ? OVERLAY_UPDATE_COEFFICIENTS : 0));
/haiku-fatelf/src/add-ons/kernel/drivers/network/sis900/
H A Dsis900.c121 write32(info->registers + SiS900_MAC_COMMAND, SiS900_MAC_CMD_Rx_ENABLE);
148 // read32(info->registers + SiS900_MAC_Tx_DESCR));
152 uint32 descriptor = read32(info->registers + SiS900_MAC_Tx_DESCR);
211 intr = read32(info->registers + SiS900_MAC_INTR_STATUS);
222 read32(info->registers + SiS900_MAC_WAKEUP_EVENT)));
225 write32(info->registers + SiS900_MAC_WAKEUP_EVENT,
251 write32(info->registers + SiS900_MAC_INTR_MASK, 0);
252 write32(info->registers + SiS900_MAC_INTR_ENABLE, 0);
259 write32(info->registers + SiS900_MAC_INTR_ENABLE, 0);
262 write32(info->registers
622 addr_t registers = isa.u.h0.base_registers[0]; local
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H A Dinterface.c35 long eepromAccess = (long)info->registers + SiS900_MAC_EEPROM_ACCESS;
114 uint32 address = info->registers + SiS900_MAC_EEPROM_ACCESS;
158 uint32 address = info->registers + SiS900_MAC_EEPROM_ACCESS;
H A Ddevice.c251 info->registers = (addr_t)pciInfo[id]->u.h0.base_registers[0];
279 write32(info->registers + SiS900_MAC_COMMAND, SiS900_MAC_CMD_Rx_ENABLE);
317 write32(info->registers + SiS900_MAC_COMMAND,
537 write32(info->registers + SiS900_MAC_COMMAND, SiS900_MAC_CMD_Tx_ENABLE);
565 struct buffer_desc *b = (void *)read32(info->registers + SiS900_MAC_Tx_DESCR);
569 dprintf("write: %d: mem = %lx : hardware = %lx\n", current, physicalAddress(&info->txDescriptor[current],sizeof(struct buffer_desc)),read32(info->registers + SiS900_MAC_Tx_DESCR));
585 write32(info->registers + SiS900_MAC_COMMAND, SiS900_MAC_CMD_Tx_ENABLE);
/haiku-fatelf/src/system/kernel/arch/x86/
H A Dioapic.cpp104 ioapic_registers* registers; member in struct:ioapic
150 ioapic.registers->io_register_select = registerSelect;
151 return ioapic.registers->io_window_register;
158 ioapic.registers->io_register_select = registerSelect;
159 ioapic.registers->io_window_register = value;
166 ioapic.registers->io_register_select = registerSelect + 1;
167 uint64 result = ioapic.registers->io_window_register;
169 ioapic.registers->io_register_select = registerSelect;
170 result |= ioapic.registers->io_window_register;
179 ioapic.registers
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H A Darch_debug.cpp319 // Since x86_64 uses registers rather than the stack for the first 6
487 arch_debug_registers* registers = debug_get_debug_registers(
489 if (registers == NULL)
491 *_bp = registers->bp;
1038 arch_debug_save_registers(arch_debug_registers* registers) argument
1042 registers->bp = (addr_t)frame->previous;
1067 arch_debug_registers* registers = debug_get_debug_registers(
1069 if (registers == NULL)
1071 bp = registers->bp;
1259 /*! Writes the contents of the CPU registers a
1287 gdb_register registers[kRegisterCount] = { local
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/haiku-fatelf/headers/private/kernel/arch/
H A Ddebug.h44 void arch_debug_save_registers(struct arch_debug_registers* registers);
/haiku-fatelf/src/system/kernel/arch/arm/
H A Darch_debug.cpp232 arch_debug_save_registers(struct arch_debug_registers* registers) argument
/haiku-fatelf/src/system/kernel/arch/mipsel/
H A Darch_debug.cpp38 arch_debug_save_registers(struct arch_debug_registers* registers) argument
/haiku-fatelf/src/apps/debugger/arch/
H A DArchitecture.cpp58 // registers. We set them respectively.
61 const Register* registers = Registers(); local
76 switch (registers[i].Type()) {

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