Searched refs:ICH_REG_X_CR (Results 1 - 4 of 4) sorted by relevance

/haiku-fatelf/src/add-ons/kernel/drivers/audio/ac97/ich/
H A Dich.c138 ich_reg_write_8(chan->regbase + ICH_REG_X_CR, CR_RPBM | CR_LVBIE | CR_IOCE);
145 ich_reg_write_8(chan->regbase + ICH_REG_X_CR, ich_reg_read_8(chan->regbase + ICH_REG_X_CR) & ~CR_RPBM);
146 ich_reg_read_8(chan->regbase + ICH_REG_X_CR); // force PCI-to-PCI bridge cache flush
154 ich_reg_write_8(chan->regbase + ICH_REG_X_CR, 0);
155 ich_reg_read_8(chan->regbase + ICH_REG_X_CR); // force PCI-to-PCI bridge cache flush
160 ich_reg_write_8(chan->regbase + ICH_REG_X_CR, CR_RR);
162 cr = ich_reg_read_8(chan->regbase + ICH_REG_X_CR);
193 ich_reg_write_8(chan_po->regbase + ICH_REG_X_CR, CR_RPBM | CR_LVBIE | CR_IOCE);
206 ich_reg_write_8(chan_po->regbase + ICH_REG_X_CR,
[all...]
H A Dhardware.h55 ICH_REG_X_CR = 0x0B enumerator in enum:ICH_X_REGISTER_OFFSETS
68 /* ICH_REG_X_CR (Control Register) Bits */
/haiku-fatelf/src/add-ons/kernel/drivers/audio/ac97/ichaudio/
H A Dhardware.h55 ICH_REG_X_CR = 0x0B enumerator in enum:ICH_X_REGISTER_OFFSETS
68 /* ICH_REG_X_CR (Control Register) Bits */
H A Dichaudio.c305 ich_reg_write_8(cookie, regbase + ICH_REG_X_CR, 0);
306 ich_reg_read_8(cookie, regbase + ICH_REG_X_CR); // force PCI-to-PCI bridge cache flush
308 ich_reg_write_8(cookie, regbase + ICH_REG_X_CR, CR_RR);
310 uint8 cr = ich_reg_read_8(cookie, regbase + ICH_REG_X_CR);

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