Searched refs:writel (Results 1 - 25 of 45) sorted by relevance

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/fuchsia/zircon/system/dev/lib/hi3660/
H A Dhi3660-usb.c20 writel(PERI_CRG_ISODIS_REFCLK_ISO_EN, peri_crg + PERI_CRG_ISODIS);
21 writel(PCTRL_CTRL3_USB_TCXO_EN | (PCTRL_CTRL3_USB_TCXO_EN << PCTRL_CTRL3_MSK_START),
26 writel(temp, pctrl + PCTRL_CTRL24);
28 writel(PERI_CRG_GT_CLK_USB3OTG_REF | PERI_CRG_GT_ACLK_USB3OTG, peri_crg + PERI_CRG_CLK_EN4);
29 writel(PERI_CRG_IP_RST_USB3OTG_MUX | PERI_CRG_IP_RST_USB3OTG_AHBIF
32 writel(PERI_CRG_IP_RST_USB3OTGPHY_POR | PERI_CRG_IP_RST_USB3OTG, peri_crg + PERI_CRG_RSTEN4);
37 writel(temp, usb3otg_bc + USB3OTG_CTRL0);
41 writel(temp, usb3otg_bc + USB3OTG_CTRL7);
46 writel(temp, usb3otg_bc + USB3OTG_CTRL2);
49 writel(PERI_CRG_IP_RST_USB3OTGPHY_PO
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H A Dhi3660-i2c.c26 writel(temp, iomcu + CLKGATE_SEPERATED_ENABLE);
37 writel(MUX_M1, iomg_pmx4 + I2C0_SCL_MUX_OFFSET); // I2C0_SCL
38 writel(MUX_M1, iomg_pmx4 + I2C0_SDA_MUX_OFFSET); // I2C0_SDA
39 writel(MUX_M1, iomg_pmx4 + I2C1_SCL_MUX_OFFSET); // I2C1_SCL
40 writel(MUX_M1, iomg_pmx4 + I2C1_SDA_MUX_OFFSET); // I2C1_SDA
43 writel(DRIVE7_02MA | PULL_UP, iocfg_pmx9 + I2C0_SCL_CFG_OFFSET);
44 writel(DRIVE7_02MA | PULL_UP, iocfg_pmx9 + I2C0_SDA_CFG_OFFSET);
45 writel(DRIVE7_02MA | PULL_UP, iocfg_pmx9 + I2C1_SCL_CFG_OFFSET);
46 writel(DRIVE7_02MA | PULL_UP, iocfg_pmx9 + I2C1_SDA_CFG_OFFSET);
H A Dhi3660-dsi.c19 writel(0x30000000, peri_crg + PERRSTDIS3);
23 writel(temp, peri_crg + TXDPHY0_REF_OFFSET);
28 writel(temp, peri_crg + TXDPHY0_CFG_OFFSET);
33 writel(temp, peri_crg + PCLK_GATE_DSI0_OFFSET);
/fuchsia/zircon/system/dev/ethernet/intel-ethernet/
H A Die.c25 #define writel(v, a) (*REG32(eth->iobase + (a)) = (v)) macro
75 writel(n, IE_RDT);
82 writel(rctl | IE_RCTL_EN, IE_RCTL);
87 writel(rctl & ~IE_RCTL_EN, IE_RCTL);
142 writel(n, IE_TDT);
157 writel(tctl | IE_TCTL_EN, IE_TCTL);
162 writel(tctl & ~IE_TCTL_EN, IE_TCTL);
167 writel(rctl | IE_RCTL_UPE, IE_RCTL);
172 writel(rctl & ~IE_RCTL_UPE, IE_RCTL);
200 writel(mdi
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/fuchsia/zircon/system/dev/lib/amlogic/
H A Daml-usb-phy-v2.c28 writel((0x30000000 | PLL_SETTING_0), reg + 0x40);
29 writel(PLL_SETTING_1, reg + 0x44);
30 writel(PLL_SETTING_2, reg + 0x48);
32 writel((0x10000000 | PLL_SETTING_0), reg + 0x40);
65 writel((val | (0x3 << 16)), reset_regs + 0x21 * 4);
69 writel(readl(reset_1) | S905D2_RESET1_USB, reset_1);
83 writel(temp, addr);
88 writel(readl(reset_1) | (1 << (16 + 0 /*i is always zero here */)), reset_1);
/fuchsia/zircon/system/dev/board/astro/
H A Dastro-usb.c67 writel(0, base + 0x38);
68 writel(PLL_SETTING_5, base + 0x34);
70 writel(PLL_SETTING_3, base + 0x50);
71 writel(PLL_SETTING_4, base + 0x10);
73 writel(PLL_SETTING_6, base + 0x38);
75 writel(PLL_SETTING_7, base + 0x38);
77 writel(PLL_SETTING_5, base + 0x34);
H A Dastro-bluetooth.c88 writel(0x016d016e, regs + S905D2_PWM_PWM_E);
89 writel(0x016d016d, regs + S905D2_PWM_E2);
90 writel(0x0a0a0609, regs + S905D2_PWM_TIME_EF);
91 writel(0x02808003, regs + S905D2_PWM_MISC_REG_EF);
/fuchsia/zircon/system/dev/pci/amlogic-pcie/
H A Daml-pcie.cpp24 writel(val, reg);
32 writel(val, reg);
66 writel(val, reg);
70 writel(val, reg);
81 writel(val, cfg);
85 writel(val, elb + PORT_LINK_CTRL_OFF);
89 writel(val, elb + PORT_LINK_CTRL_OFF);
93 writel(val, elb + PORT_LINK_CTRL_OFF);
97 writel(val, elb + GEN2_CTRL_OFF);
101 writel(va
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H A Daml-pcie-clk.cpp86 writel(AXG_MIPI_CNTL0, regs + 0);
87 writel(AXG_PCIE_PLL_CNTL0, regs + PCIE_PLL_CNTL0);
88 writel(AXG_PCIE_PLL_CNTL1, regs + PCIE_PLL_CNTL1);
89 writel(AXG_PCIE_PLL_CNTL2, regs + PCIE_PLL_CNTL2);
90 writel(AXG_PCIE_PLL_CNTL3, regs + PCIE_PLL_CNTL3);
91 writel(AXG_PCIE_PLL_CNTL4, regs + PCIE_PLL_CNTL4);
92 writel(AXG_PCIE_PLL_CNTL5, regs + PCIE_PLL_CNTL5);
93 writel(AXG_PCIE_PLL_CNTL6, regs + PCIE_PLL_CNTL6);
/fuchsia/zircon/kernel/dev/power/hisi/
H A Dpower.c29 writel(temp, pmu + PMU_HRST_OFFSET);
31 writel(SCTRL_DDR_BYPASS, sctrl + SCTRL_PEREN1_OFFSET);
32 writel(0xdeadbeef, sctrl + SCTRL_REBOOT_OFFSET);
/fuchsia/zircon/system/dev/lib/amlogic/include/soc/aml-common/
H A Daml-gpu.h23 #define WRITE32_GPU_REG(offset, value) writel(value, (uint32_t*)gpu->gpu_buffer.vaddr + offset)
26 #define WRITE32_HIU_REG(offset, value) writel(value, (uint32_t*)gpu->hiu_buffer.vaddr + offset)
29 #define WRITE32_PRESET_REG(offset, value) writel(value, (uint32_t*)gpu->preset_buffer.vaddr + offset)
/fuchsia/zircon/system/dev/board/gauss/
H A Dgauss-usb.c82 writel(temp, addr);
86 writel(temp, addr);
94 writel(temp, addr + USB_R1_OFFSET);
100 writel(temp, addr + USB_R5_OFFSET);
/fuchsia/zircon/system/dev/board/vim/
H A Dvim-usb.c83 writel(temp, addr);
87 writel(temp, addr);
95 writel(temp, addr + USB_R1_OFFSET);
101 writel(temp, addr + USB_R5_OFFSET);
H A Dvim-uart.c138 writel(0x016d016e, regs + S912_PWM_PWM_E);
139 writel(0x016d016d, regs + S912_PWM_E2);
140 writel(0x0a0a0609, regs + S912_PWM_TIME_EF);
141 writel(0x02808003, regs + S912_PWM_MISC_REG_EF);
/fuchsia/zircon/system/ulib/ddk/include/hw/
H A Dreg.h27 static inline void writel(uint32_t v, volatile void* a) { function
63 static inline void writel(uint32_t v, volatile void* a) { function
90 writel((readl(addr) & ~(((1 << (width)) - 1) << (startbit))) | ((val) << (startbit)), (addr))
100 #define set_bitsl(v, a) writel(readl(a) | (v), (a))
101 #define clr_bitsl(v, a) writel(readl(a) & ~(v), (a))
/fuchsia/zircon/system/dev/nand/aml-rawnand/
H A Daml-rawnand.h55 writel(((readl(_reg) & ~(((1L << (_len)) - 1) << (_start))) | ((uint32_t)((_value) & ((1L << (_len)) - 1)) << (_start))), _reg);
63 writel(val, reg + P_NAND_CFG);
82 writel(cmd, reg + P_NAND_CMD);
H A Daml-rawnand.c140 writel(cmd, reg + P_NAND_CMD);
176 writel(cmd, reg + P_NAND_CMD);
191 writel(cmd, reg + P_NAND_CMD);
209 writel(cmd, reg + P_NAND_CMD);
227 writel(cmd, reg + P_NAND_CMD);
372 writel(cfg, reg + P_NAND_CFG);
375 writel(cmd, reg + P_NAND_CMD);
378 writel(cmd, reg + P_NAND_CMD);
402 writel(cmd, reg + P_NAND_CMD);
451 writel(cl
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/fuchsia/zircon/bootloader/include/
H A Dreg.h18 #define writel(v, a) (*REG32(a) = (v)) macro
/fuchsia/zircon/system/dev/block/imx-sdhci/
H A Dimx-sdhci.c298 writel(0, &dev->regs->int_signal_en);
379 writel(*wrd, &dev->regs->data_buff_acc_port); //TODO: Can't write if DMA is enabled
641 writel((uint32_t)desc_phys, &regs->adma_sys_addr);
644 writel(0, &regs->adma_err_status);
654 writel(blksiz | (blkcnt << 16), &regs->blk_att);
655 writel((blksiz/4) | (blksiz/4) << 16, &dev->regs->wtmk_lvl);
657 writel(arg, &regs->cmd_arg);
660 writel(0xFFFFFFFF, &regs->int_status);
664 writel(error_interrupts | dma_normal_interrupts, &regs->int_signal_en);
665 writel(error_interrupt
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/fuchsia/zircon/system/dev/board/imx8mevk/
H A Dimx8mevk-gpu.c53 writel(0x3, ccm_regs + kOffset);
75 writel(reg_val, ccm_regs + kOffset);
98 writel(reg_val, ccm_regs + kOffset);
122 writel(reg_val, ccm_regs + kOffset);
145 writel(reg_val, ccm_regs + kOffset);
H A Dimx8mevk-usb.c125 writel(reg, regs + USB_PHY_CTRL1);
129 writel(reg, regs + USB_PHY_CTRL0);
133 writel(reg, regs + USB_PHY_CTRL2);
137 writel(reg, regs + USB_PHY_CTRL1);
/fuchsia/zircon/kernel/dev/hdcp/amlogic_s912/
H A Dhdcp.c34 #define WRITE32_PRESET_REG(a, v) writel(v, preset_base + a)
37 #define WRITE32_HDMITX_REG(a, v) writel(v, hdmitx_base + a)
40 #define WRITE32_HHI_REG(a, v) writel(v, hiu_base + a)
/fuchsia/zircon/system/dev/display/vim-display/
H A Dhdmitx.h29 #define WRITE32_PRESET_REG(a, v) writel(v, (uint8_t*)io_buffer_virt(&display->mmio_preset) + a)
32 #define WRITE32_HDMITX_REG(a, v) writel(v, (uint8_t*)io_buffer_virt(&display->mmio_hdmitx) + a)
35 #define WRITE32_HHI_REG(a, v) writel(v, (uint8_t*)io_buffer_virt(&display->mmio_hiu) + a)
38 #define WRITE32_VPU_REG(a, v) writel(v, (uint8_t*)io_buffer_virt(&display->mmio_vpu) + a)
41 #define WRITE32_HDMITX_SEC_REG(a, v) writel(v, (uint8_t*)io_buffer_virt(&display->mmio_hdmitx_sec) + a)
44 #define WRITE32_CBUS_REG(a, v) writel(v, (uint8_t*)io_buffer_virt(&display->mmio_cbus) + 0x400+ a)
/fuchsia/zircon/kernel/include/
H A Dreg.h25 #define writel(v, a) (*REG32(a) = (v)) macro
/fuchsia/zircon/system/dev/ethernet/aml-ethernet-s912/
H A Daml-ethernet.cpp139 writel(0x1621, offset_ptr<uint32_t>(pregs, PER_ETH_REG0));
140 writel(0x20000, offset_ptr<uint32_t>(pregs, PER_ETH_REG1));
142 writel(REG2_ETH_REG2_REVERSED | REG2_INTERNAL_PHY_ID,
145 writel(REG3_CLK_IN_EN | REG3_ETH_REG3_19_RESVERD |

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