/fuchsia/zircon/system/dev/clk/amlogic-clk/ |
H A D | aml-axg-blocks.h | 19 {.reg = AXG_HHI_GCLK_MPEG0, .bit = 0}, // CLK_AXG_DDR 20 {.reg = AXG_HHI_GCLK_MPEG0, .bit = 2}, // CLK_AXG_AUDIO_LOCKER 21 {.reg = AXG_HHI_GCLK_MPEG0, .bit = 3}, // CLK_AXG_MIPI_DSI_HOST 22 {.reg = AXG_HHI_GCLK_MPEG0, .bit = 5}, // CLK_AXG_ISA 23 {.reg = AXG_HHI_GCLK_MPEG0, .bit = 6}, // CLK_AXG_PL301 24 {.reg = AXG_HHI_GCLK_MPEG0, .bit = 7}, // CLK_AXG_PERIPHS 25 {.reg = AXG_HHI_GCLK_MPEG0, .bit = 8}, // CLK_AXG_SPICC_0 26 {.reg = AXG_HHI_GCLK_MPEG0, .bit = 9}, // CLK_AXG_I2C 27 {.reg = AXG_HHI_GCLK_MPEG0, .bit = 12}, // CLK_AXG_RNG0 28 {.reg [all...] |
H A D | aml-gxl-blocks.h | 17 {.reg = GXL_HHI_GCLK_MPEG0, .bit = 0}, // CLK_GXL_DDR 18 {.reg = GXL_HHI_GCLK_MPEG0, .bit = 1}, // CLK_GXL_DOS 19 {.reg = GXL_HHI_GCLK_MPEG0, .bit = 5}, // CLK_GXL_ISA 20 {.reg = GXL_HHI_GCLK_MPEG0, .bit = 6}, // CLK_GXL_PL301 21 {.reg = GXL_HHI_GCLK_MPEG0, .bit = 7}, // CLK_GXL_PERIPHS 22 {.reg = GXL_HHI_GCLK_MPEG0, .bit = 8}, // CLK_GXL_SPICC 23 {.reg = GXL_HHI_GCLK_MPEG0, .bit = 9}, // CLK_GXL_I2C 24 {.reg = GXL_HHI_GCLK_MPEG0, .bit = 10}, // CLK_GXL_SANA 25 {.reg = GXL_HHI_GCLK_MPEG0, .bit = 11}, // CLK_GXL_SMART_CARD 26 {.reg [all...] |
H A D | aml-clk-blocks.h | 10 uint32_t reg; // Offset from Clock Base Addr (in 4 byte words) member in struct:meson_clk_gate
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/fuchsia/zircon/third_party/ulib/ngunwind/src/arm/ |
H A D | regname.c | 84 unw_regname (unw_regnum_t reg) argument 86 if (reg < (unw_regnum_t) ARRAY_SIZE (regname)) 87 return regname[reg];
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H A D | Gstash_frame.c | 40 rs->reg[DWARF_CFA_REG_COLUMN].where, 41 (int) rs->reg[DWARF_CFA_REG_COLUMN].val, 42 (int) rs->reg[DWARF_CFA_OFF_COLUMN].val, 44 rs->reg[R7].where, (int) rs->reg[R7].val, (int) DWARF_GET_LOC(d->loc[R7]), 45 rs->reg[LR].where, (int) rs->reg[LR].val, (int) DWARF_GET_LOC(d->loc[LR]), 46 rs->reg[SP].where, (int) rs->reg[SP].val, (int) DWARF_GET_LOC(d->loc[SP])); 55 && (rs->reg[DWARF_CFA_REG_COLUM [all...] |
H A D | Ginit.c | 38 uc_addr (unw_tdep_context_t *uc, int reg) argument 42 if (reg >= UNW_ARM_R0 && reg < UNW_ARM_R0 + 16) 43 return &uc->uc_mcontext.arm_r0 + (reg - UNW_ARM_R0); 134 access_reg (unw_addr_space_t as, unw_regnum_t reg, unw_word_t *val, int write, argument 140 if (unw_is_fpreg (reg)) 143 if (!(addr = uc_addr (uc, reg))) 149 Debug (12, "%s <- %" PRIxPTR "\n", unw_regname (reg), *val); 154 Debug (12, "%s -> %" PRIxPTR "\n", unw_regname (reg), *val); 159 Debug (1, "bad register number %u\n", reg); 164 access_fpreg(unw_addr_space_t as, unw_regnum_t reg, unw_fpreg_t *val, int write, void *arg) argument [all...] |
/fuchsia/zircon/third_party/ulib/ngunwind/src/x86_64/ |
H A D | regname.c | 50 unw_regname (unw_regnum_t reg) argument 52 if (reg < (unw_regnum_t) ARRAY_SIZE (regname)) 53 return regname[reg];
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H A D | Gstash_frame.c | 38 rs->reg[DWARF_CFA_REG_COLUMN].where, 39 rs->reg[DWARF_CFA_REG_COLUMN].val, 40 rs->reg[DWARF_CFA_OFF_COLUMN].val, 42 rs->reg[RBP].where, rs->reg[RBP].val, DWARF_GET_LOC(d->loc[RBP]), 43 rs->reg[RSP].where, rs->reg[RSP].val, DWARF_GET_LOC(d->loc[RSP])); 51 && (rs->reg[DWARF_CFA_REG_COLUMN].where == DWARF_WHERE_REG) 52 && (rs->reg[DWARF_CFA_REG_COLUMN].val == RBP 53 || rs->reg[DWARF_CFA_REG_COLUM [all...] |
/fuchsia/zircon/third_party/ulib/ngunwind/src/aarch64/ |
H A D | Gstash_frame.c | 40 rs->reg[DWARF_CFA_REG_COLUMN].where, 41 rs->reg[DWARF_CFA_REG_COLUMN].val, 42 rs->reg[DWARF_CFA_OFF_COLUMN].val, 44 rs->reg[FP].where, rs->reg[FP].val, DWARF_GET_LOC(d->loc[FP]), 45 rs->reg[LR].where, rs->reg[LR].val, DWARF_GET_LOC(d->loc[LR]), 46 rs->reg[SP].where, rs->reg[SP].val, DWARF_GET_LOC(d->loc[SP])); 55 && (rs->reg[DWARF_CFA_REG_COLUM [all...] |
H A D | Gregs.c | 43 tdep_access_reg (struct cursor *c, unw_regnum_t reg, unw_word_t *valp, argument 49 switch (reg) 55 mask = 1 << reg; 58 c->dwarf.eh_args[reg] = *valp; 64 *valp = c->dwarf.eh_args[reg]; 68 loc = c->dwarf.loc[reg]; 100 loc = c->dwarf.loc[reg]; 110 Debug (1, "bad register number %u\n", reg); 121 tdep_access_fpreg (struct cursor *c, unw_regnum_t reg, unw_fpreg_t *valp, argument 124 Debug (1, "bad register number %u\n", reg); [all...] |
H A D | Ginit.c | 39 uc_addr (ucontext_t *uc, int reg) argument 43 if (reg >= UNW_AARCH64_X0 && reg <= UNW_AARCH64_V31) 44 return &uc->uc_mcontext.regs[reg - UNW_AARCH64_X0]; 86 access_reg (unw_addr_space_t as, unw_regnum_t reg, unw_word_t *val, int write, argument 92 if (unw_is_fpreg (reg)) 95 if (!(addr = uc_addr (uc, reg))) 101 Debug (12, "%s <- %lx\n", unw_regname (reg), *val); 106 Debug (12, "%s -> %lx\n", unw_regname (reg), *val); 111 Debug (1, "bad register number %u\n", reg); 116 access_fpreg(unw_addr_space_t as, unw_regnum_t reg, unw_fpreg_t *val, int write, void *arg) argument [all...] |
H A D | regname.c | 100 unw_regname (unw_regnum_t reg) argument 102 if (reg < (unw_regnum_t) ARRAY_SIZE (regname) && regname[reg] != NULL) 103 return regname[reg];
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/fuchsia/zircon/system/ulib/zircon/ |
H A D | zircon-syscall-x86-64.S | 14 .macro push_reg reg 15 push \reg 17 .cfi_rel_offset \reg, 0 19 .macro pop_reg reg 20 pop \reg 22 .cfi_same_value \reg
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/fuchsia/zircon/third_party/ulib/ngunwind/include/ngunwind/private/ |
H A D | dwarf-config.h | 35 #define dwarf_to_unw_regnum(reg) (((reg) <= UNW_ARM_R15) ? (reg) : 0) 45 #define dwarf_to_unw_regnum(reg) (((reg) <= UNW_AARCH64_V31) ? (reg) : 0)
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/fuchsia/zircon/system/dev/clk/hisi3660/ |
H A D | hisi3660-clk.c | 5 #include <hw/reg.h> 26 { .reg = 0x0, .bit = 0, .flags = HISI_CLK_FLAG_BANK_PERI }, 27 { .reg = 0x0, .bit = 21, .flags = HISI_CLK_FLAG_BANK_PERI }, 28 { .reg = 0x0, .bit = 30, .flags = HISI_CLK_FLAG_BANK_PERI }, 29 { .reg = 0x0, .bit = 31, .flags = HISI_CLK_FLAG_BANK_PERI }, 30 { .reg = 0x10, .bit = 0, .flags = HISI_CLK_FLAG_BANK_PERI }, 31 { .reg = 0x10, .bit = 1, .flags = HISI_CLK_FLAG_BANK_PERI }, 32 { .reg = 0x10, .bit = 2, .flags = HISI_CLK_FLAG_BANK_PERI }, 33 { .reg = 0x10, .bit = 3, .flags = HISI_CLK_FLAG_BANK_PERI }, 34 { .reg [all...] |
/fuchsia/zircon/system/dev/display/astro-display/ |
H A D | osd.cpp | 316 uint32_t reg = 0; local 320 reg = VPU_VIU_VENC_MUX_CTRL; 321 DISP_INFO("reg[0x%x]: 0x%08x\n", reg, READ32_REG(VPU, reg)); 322 reg = VPU_VPP_MISC; 323 DISP_INFO("reg[0x%x]: 0x%08x\n", reg, READ32_REG(VPU, reg)); 324 reg [all...] |
/fuchsia/zircon/kernel/target/arm64/boot-shim/ |
H A D | mt8167s_ref-uart.c | 12 #define UARTREG(reg) (*(volatile uint32_t*)(0x11005000 + (reg)))
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/fuchsia/zircon/third_party/ulib/musl/include/sys/ |
H A D | reg.h | 6 #include <bits/reg.h>
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/fuchsia/zircon/system/utest/thread-initial-state/ |
H A D | x86-64.S | 7 .macro check_general_purpose reg 8 cmpq $0, \reg 12 .macro check_xmm reg 17 movdqu \reg, -16(%rsp) 24 .macro check_ymm reg 25 vptest \reg, \reg 29 .macro check_mm reg 30 movq \reg, %rax 35 .macro check_segment reg [all...] |
/fuchsia/zircon/kernel/arch/arm64/include/arch/ |
H A D | asm_macros.h | 12 .macro movlit reg, literal 13 mov \reg, #((\literal) & 0xffff) variable 15 movk \reg, #(((\literal) >> 16) & 0xffff), lsl #16 variable 18 movk \reg, #(((\literal) >> 32) & 0xffff), lsl #32 variable 21 movk \reg, #(((\literal) >> 48) & 0xffff), lsl #48 variable 59 .macro adr_global reg, symbol 60 adrp \reg, \symbol variable 61 add \reg, \reg, #:lo12:\symbol variable 64 .macro movabs reg, symbo 68 ldr \\reg, =\\symbol variable 77 .macro tbzmask, reg, mask, label, shift=0 variable 87 .macro tbnzmask, reg, mask, label, shift=0 variable [all...] |
/fuchsia/zircon/system/dev/display/vim-display/ |
H A D | vpp.cpp | 22 #include <hw/reg.h> 27 uint32_t reg = 0; local 31 reg = VPU_VPU_VIU_VENC_MUX_CTRL; 32 DISP_INFO("reg[0x%x]: 0x%08x\n", (reg >> 2), READ32_VPU_REG(reg)); 33 reg = VPU_VPP_MISC; 34 DISP_INFO("reg[0x%x]: 0x%08x\n", (reg >> 2), READ32_VPU_REG(reg)); [all...] |
/fuchsia/zircon/system/utest/region-alloc/ |
H A D | common.h | 200 ralloc_region_t reg; // Region to add member in struct:__anon1454 210 { .reg = { .base = 0x10000, .size = 0x1000 }, .ovl = false, .cnt = 1, .res = ZX_OK }, 211 { .reg = { .base = 0x10000, .size = 0x1000 }, .ovl = false, .cnt = 1, .res = ZX_ERR_INVALID_ARGS }, 212 { .reg = { .base = 0x10000, .size = 0x1000 }, .ovl = true, .cnt = 1, .res = ZX_OK }, 217 { .reg = { .base = 0xF800, .size = 0x800 }, .ovl = false, .cnt = 1, .res = ZX_OK }, 218 { .reg = { .base = 0xF800, .size = 0x800 }, .ovl = true, .cnt = 1, .res = ZX_OK }, 222 { .reg = { .base = 0x11000, .size = 0x800 }, .ovl = false, .cnt = 1, .res = ZX_OK }, 223 { .reg = { .base = 0x11000, .size = 0x800 }, .ovl = true, .cnt = 1, .res = ZX_OK }, 228 { .reg = { .base = 0xF000, .size = 0x801 }, .ovl = false, .cnt = 1, .res = ZX_ERR_INVALID_ARGS }, 229 { .reg 280 ralloc_region_t reg; // Region to add or subtract member in struct:__anon1455 [all...] |
/fuchsia/zircon/kernel/arch/x86/include/arch/ |
H A D | asm_macros.h | 12 .macro push_reg reg 13 pushq \reg 15 .cfi_rel_offset \reg, 0 18 .macro pop_reg reg 19 popq \reg 21 .cfi_same_value \reg
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/fuchsia/zircon/system/dev/audio/gauss-pdm-input/ |
H A D | a113-audio-device.h | 31 uint32_t a113_ee_audio_read(a113_audio_device_t* audio_device, uint32_t reg); 32 void a113_ee_audio_write(a113_audio_device_t* audio_device, uint32_t reg, uint32_t value); 33 void a113_ee_audio_update_bits(a113_audio_device_t* audio_device, uint32_t reg, 36 uint32_t a113_pdm_read(a113_audio_device_t* audio_device, uint32_t reg); 37 void a113_pdm_write(a113_audio_device_t* audio_device, uint32_t reg, uint32_t val); 38 void a113_pdm_update_bits(a113_audio_device_t* audio_device, uint32_t reg,
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/fuchsia/zircon/system/ulib/ddk/include/ddk/protocol/ |
H A D | ethernet_mac.h | 20 zx_status_t (*mdio_read)(void* ctx, uint32_t reg, uint32_t* val); 21 zx_status_t (*mdio_write)(void* ctx, uint32_t reg, uint32_t val); 31 uint32_t reg, 33 return eth_mac->ops->mdio_read(eth_mac->ctx, reg, val); 37 uint32_t reg, 39 return eth_mac->ops->mdio_write(eth_mac->ctx, reg, val); 30 mdio_read(const eth_mac_protocol_t* eth_mac, uint32_t reg, uint32_t* val) argument 36 mdio_write(const eth_mac_protocol_t* eth_mac, uint32_t reg, uint32_t val) argument
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