Searched refs:pipe (Results 1 - 25 of 30) sorted by relevance

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/fuchsia/zircon/system/dev/display/intel-i915/
H A Ddisplay-device.cpp185 if (!DdiModeset(info_, pipe_->pipe(), pipe_->transcoder())) {
199 bool DisplayDevice::AttachPipe(Pipe* pipe) { argument
200 if (pipe == pipe_) {
208 if (pipe) {
209 pipe->AttachToDisplay(id_, controller()->igd_opregion().IsEdp(ddi()));
212 PipeConfigPreamble(info_, pipe->pipe(), pipe->transcoder());
213 pipe->ApplyModeConfig(info_);
214 PipeConfigEpilogue(info_, pipe
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H A Dinterrupts.h13 #include "registers-pipe.h"
29 void EnablePipeVsync(registers::Pipe pipe, bool enable);
36 void HandlePipeInterrupt(registers::Pipe pipe, zx_time_t timestamp);
H A Ddisplay-device.h14 #include "pipe.h"
17 #include "registers-pipe.h"
39 bool AttachPipe(Pipe* pipe);
64 Pipe* pipe() const { return pipe_; } function in class:i915::DisplayDevice
81 registers::Pipe pipe, registers::Trans trans) = 0;
86 // Attaching a pipe to a display or configuring a pipe after display mode change has
87 // 3 steps. The second step is generic pipe configuration, whereas PipeConfigPreamble
91 registers::Pipe pipe, registers::Trans trans) = 0;
93 registers::Pipe pipe, register
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H A Dhdmi-display.h43 registers::Pipe pipe, registers::Trans trans) final;
45 registers::Pipe pipe, registers::Trans trans) final;
47 registers::Pipe pipe, registers::Trans trans) final;
H A Dpower.h9 #include "registers-pipe.h"
45 PowerWellRef GetPipePowerWellRef(registers::Pipe pipe);
H A Dpipe.h17 #include "registers-pipe.h"
27 Pipe(Controller* device, registers::Pipe pipe);
42 registers::Pipe pipe() const { return pipe_; } function in class:i915::Pipe
H A Dinterrupts.cpp90 void Interrupts::HandlePipeInterrupt(registers::Pipe pipe, zx_time_t timestamp) { argument
91 registers::PipeRegs regs(pipe);
96 controller_->HandlePipeVsync(pipe, timestamp);
100 void Interrupts::EnablePipeVsync(registers::Pipe pipe, bool enable) { argument
101 registers::PipeRegs regs(pipe);
H A Ddp-display.h53 registers::Pipe pipe, registers::Trans trans) final;
55 registers::Pipe pipe, registers::Trans trans) final;
57 registers::Pipe pipe, registers::Trans trans) final;
H A Dpower.cpp62 PowerWellRef Power::GetPipePowerWellRef(registers::Pipe pipe) { argument
63 return PowerWellRef(this, pipe == registers::PIPE_A ? PowerWell1 : PowerWell2);
H A Drules.mk22 $(LOCAL_DIR)/pipe.cpp \
H A Dintel-i915.cpp36 #include "registers-pipe.h"
234 // Make sure the display's resources get freed before reallocating the pipe buffers
254 void Controller::HandlePipeVsync(registers::Pipe pipe, zx_time_t timestamp) { argument
265 if (pipes_[pipe].in_use()) {
266 id = pipes_[pipe].attached_display_id();
268 registers::PipeRegs regs(pipe);
442 void Controller::ResetPipe(registers::Pipe pipe) { argument
443 registers::PipeRegs pipe_regs(pipe);
458 plane_buffers_[pipe][plane_num].start = registers::PlaneBufCfg::kBufferCount;
598 auto pipe local
712 auto pipe = registers::PIPE_INVALID; local
874 GetPlaneLayer(registers::Pipe pipe, uint32_t plane, const display_config_t** configs, uint32_t display_count, const layer_t** layer_out) argument
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H A Dpipe.cpp13 #include "pipe.h"
73 Pipe::Pipe(Controller* controller, registers::Pipe pipe) argument
74 : controller_(controller), pipe_(pipe) {}
139 registers::PipeRegs pipe_regs(pipe());
185 // If we're reusing hardware state, make sure the pipe source size matches
275 registers::PipeRegs pipe_regs(pipe());
322 if (scaled_planes_[pipe()][plane_num]) {
323 uint32_t scaler_idx = scaled_planes_[pipe()][plane_num] - 1;
326 scaled_planes_[pipe()][plane_num] = 0;
356 scaled_planes_[pipe()][plane_nu
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H A Dintel-i915.h24 #include "pipe.h"
29 #include "registers-pipe.h"
120 void HandlePipeVsync(registers::Pipe pipe, zx_time_t timestamp);
123 void ResetPipe(registers::Pipe pipe) __TA_NO_THREAD_SAFETY_ANALYSIS;
144 // Gets the layer_t* config for the given pipe/plane. Return false if there is no layer.
145 bool GetPlaneLayer(registers::Pipe pipe, uint32_t plane,
162 // Reallocates the pipe buffers when a pipe comes online/goes offline. This is a
H A Ddp-display.cpp18 #include "registers-pipe.h"
866 static registers::Trans select_trans(registers::Ddi ddi, registers::Pipe pipe) { argument
870 return static_cast<registers::Trans>(pipe);
1120 registers::Pipe pipe, registers::Trans trans) {
1125 registers::Pipe pipe, registers::Trans trans) {
1181 registers::Pipe pipe, registers::Trans trans) {
1198 ddi_func.set_edp_input_select(pipe == registers::PIPE_A ? ddi_func.kPipeA :
1199 (pipe == registers::PIPE_B ? ddi_func.kPipeB : ddi_func.kPipeC));
1119 DdiModeset(const display_mode_t& mode, registers::Pipe pipe, registers::Trans trans) argument
1124 PipeConfigPreamble(const display_mode_t& mode, registers::Pipe pipe, registers::Trans trans) argument
1180 PipeConfigEpilogue(const display_mode_t& mode, registers::Pipe pipe, registers::Trans trans) argument
H A Dhdmi-display.cpp15 #include "registers-pipe.h"
549 registers::Pipe pipe, registers::Trans trans) {
550 controller()->ResetPipe(pipe);
628 registers::Pipe pipe, registers::Trans trans) {
640 registers::Pipe pipe, registers::Trans trans) {
548 DdiModeset(const display_mode_t& mode, registers::Pipe pipe, registers::Trans trans) argument
627 PipeConfigPreamble(const display_mode_t& mode, registers::Pipe pipe, registers::Trans trans) argument
639 PipeConfigEpilogue(const display_mode_t& mode, registers::Pipe pipe, registers::Trans trans) argument
H A Dregisters-pipe.h332 // An instance of PipeRegs represents the registers for a particular pipe.
340 PipeRegs(Pipe pipe) : pipe_(pipe) { }
/fuchsia/zircon/system/utest/fbl/
H A Dunique_fd_tests.cpp39 EXPECT_EQ(pipe(pipes), 0);
84 EXPECT_EQ(pipe(pipes), 0);
101 EXPECT_EQ(pipe(pipes), 0);
121 EXPECT_EQ(pipe(pipes), 0);
140 EXPECT_EQ(pipe(pipes), 0);
161 EXPECT_EQ(pipe(pipes), 0);
163 EXPECT_EQ(pipe(other_pipes), 0);
/fuchsia/zircon/system/utest/stdio/
H A Dutil.c15 // readable: is the pipe readable on the child side?
19 if ((r = pipe(pipe_fds)) != 0) { // Initially gives [reader, writer]
H A Dstdio.c34 ASSERT_EQ(pipe(fds), 0, "pipe creation failed");
36 ASSERT_GT(write(fds[1], "hello", 5), 0, "pipe write failed");
39 ASSERT_GT(read(fds[0], buffer, 5), 0, "pipe read failed");
41 ASSERT_EQ(strncmp(buffer, "hello", 5), 0, "Incorrect buffer read from pipe");
44 ASSERT_EQ(errno, ESPIPE, "lseek error should have been pipe-related");
86 // stdio pipe fds [ours, theirs]
91 ASSERT_EQ(stdio_pipe(stdin_fds, true), 0, "stdin pipe creation failed");
92 ASSERT_EQ(stdio_pipe(stdout_fds, false), 0, "stdout pipe creation failed");
93 ASSERT_EQ(stdio_pipe(stderr_fds, false), 0, "stderr pipe creatio
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/fuchsia/zircon/system/ulib/fdio/
H A Drules.mk24 $(LOCAL_DIR)/pipe.c \
H A Dremoteio.c68 if (info->pipe.s != ZX_HANDLE_INVALID) {
69 *out = info->pipe.s;
288 handle_target = &info->extra.pipe.s;
369 static_assert(__builtin_offsetof(zxrio_node_info_t, pipe.s) ==
370 __builtin_offsetof(fuchsia_io_NodeInfo, pipe.socket), "Unaligned Pipe");
473 // Without a control plane, the socket is a pipe.
551 if (info->pipe.s == ZX_HANDLE_INVALID) {
556 return fdio_acquire_socket(info->pipe.s, out);
600 info.pipe.s = handles[0];
/fuchsia/zircon/system/ulib/fdio/include/lib/fdio/
H A Dremoteio.h85 } pipe; member in union:__anon1030::__anon1031
/fuchsia/zircon/system/utest/fdio/
H A Dfdio_handle_fd.c56 int status = pipe(fds);
57 ASSERT_EQ(status, 0, "pipe() failed");
60 ASSERT_EQ(fstat(fds[0], &st), 0, "fstat() on pipe failed");
62 ASSERT_EQ(fstat(fds[1], &st), 0, "fstat() on pipe failed");
114 int status = pipe(fds);
115 ASSERT_EQ(status, 0, "pipe() failed");
150 int status = pipe(fds);
151 ASSERT_EQ(status, 0, "pipe() failed");
166 int status = pipe(fds);
167 ASSERT_EQ(status, 0, "pipe() faile
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/fuchsia/zircon/system/core/netsvc/
H A Dtftp.c149 // Pushes all data from the paver buffer (filled by netsvc) into the paver input pipe. When
239 if (pipe(fds)) {
244 if (pipe(logfds)) {
/fuchsia/zircon/third_party/uapp/dash/src/
H A Dredir.c65 # define PIPESIZE 4096 /* amount of buffering in a pipe */
291 * data to a pipe. If the document is short, we can stuff the data in
292 * the pipe without forking.
302 if (pipe(pip) < 0)

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