display/intel-i915/intel-i915.cpp

36 #include "registers-pipe.h"
234         // Make sure the display's resources get freed before reallocating the pipe buffers
254 void Controller::HandlePipeVsync(registers::Pipe pipe, zx_time_t timestamp) {
265     if (pipes_[pipe].in_use()) {
266         id = pipes_[pipe].attached_display_id();
268         registers::PipeRegs regs(pipe);
442 void Controller::ResetPipe(registers::Pipe pipe) {
443     registers::PipeRegs pipe_regs(pipe);
458         plane_buffers_[pipe][plane_num].start = registers::PlaneBufCfg::kBufferCount;
598     auto pipe = registers::PIPE_INVALID;
604             pipe = registers::PIPE_A;
606             pipe = registers::PIPE_B;
608             pipe = registers::PIPE_C;
616                 pipe = registers::kPipes[j];
622     if (pipe == registers::PIPE_INVALID) {
657     device->AttachPipe(&pipes_[pipe]);
712         auto pipe = registers::PIPE_INVALID;
715                 pipe = p.pipe();
720         if (pipe == registers::PIPE_INVALID) {
874 bool Controller::GetPlaneLayer(registers::Pipe pipe, uint32_t plane,
877     if (!pipes_[pipe].in_use()) {
880     uint64_t disp_id = pipes_[pipe].attached_display_id();
925         registers::Pipe pipe = registers::kPipes[pipe_num];
930             if (!GetPlaneLayer(pipe, plane_num, display_configs, display_count, &layer)) {
1028     // Do the actual allocation, using the buffers that are asigned to each pipe.
1043             registers::Pipe pipe = registers::kPipes[pipe_num];
1044             registers::PipeRegs pipe_regs(pipe);
1047             // worry about overlaps when updating planes during a pipe allocation.
1092         registers::Pipe pipe = registers::kPipes[pipe_num];
1095             if (!GetPlaneLayer(pipe, plane_num, display_configs, display_count, &layer)) {
1110                 // Other layers don't use pipe/planes, so GetPlaneLayer should have returned false
1123         // Allocate buffers to each pipe, but save the old allocation to use
1144     // It's not necessary to flush the buffer changes since the pipe allocs didn't change
1175             // Look through all the other active pipe allocations for overlap
1199                 // Flush the pipe allocation, wait for it to be active, and update
1262         // Either the pipe pixel rate or the link pixel rate can't support a simple
1269         // Compute the maximum pipe pixel rate with the desired scaling. If the max rate
1517         if (display != nullptr && display->pipe() != nullptr) {
1518             alloc[display->pipe()->pipe()] = display_config[i]->display_id;
1524         if (display != nullptr && display->pipe() == nullptr) {
1546         // pipe allocation should always succeed.
1556         Pipe* pipe = nullptr;
1558             pipe = display->pipe();
1559             if (pipe == nullptr) {
1562                         pipe = pipes_ + i;
1569         if (display->AttachPipe(pipe)) {
1595             if (display->pipe()) {
1596                 ResetPipe(display->pipe()->pipe());
1867                 if (display->pipe() == nullptr) {
1871                 registers::PipeRegs pipe_regs(display->pipe()->pipe());
1918     for (auto& pipe : pipes_) {
1919         pipe.Init();