Searched refs:REG_4 (Results 1 - 3 of 3) sorted by relevance

/fuchsia/zircon/system/dev/gpio/aml-gxl-gpio/
H A Ds905-blocks.h132 #define REG_4 S905_PERIPHS_PIN_MUX_4 macro
162 { .regs = { REG_4, 0, REG_3, REG_3 }, .bits = { 7, 0, 30, 10 }, },
163 { .regs = { REG_4, 0, REG_3, REG_3 }, .bits = { 6, 0, 29, 7 }, },
166 { .regs = { 0, REG_4, REG_4 }, .bits = { 0, 13, 17 }, },
167 { .regs = { 0, REG_4, REG_4 }, .bits = { 0, 12, 16 }, },
168 { .regs = { 0, REG_4, REG_4 }, .bits = { 0, 11, 15 }, },
169 { .regs = { 0, REG_4, REG_
326 #undef REG_4 macro
[all...]
H A Ds912-blocks.h119 #define REG_4 S912_PERIPHS_PIN_MUX_4 macro
253 { .regs = { REG_4, REG_3, REG_3, REG_3 }, .bits = { 23, 14, 31, 19 }, },
254 { .regs = { REG_4, REG_3, REG_3, REG_3 }, .bits = { 22, 13, 30, 18 }, },
255 { .regs = { REG_4, 0, REG_3, REG_3 }, .bits = { 21, 0, 29, 17 }, },
256 { .regs = { REG_4, REG_3, REG_3, REG_3 }, .bits = { 20, 12, 28, 16 }, },
257 { .regs = { REG_4, REG_3, REG_3, REG_3 }, .bits = { 19, 11, 27, 15 }, },
258 { .regs = { REG_4, REG_3, REG_3 }, .bits = { 18, 11, 26 }, },
259 { .regs = { REG_4, REG_3, REG_3, REG_4 }, .bits = { 17, 11, 25, 9 }, },
260 { .regs = { REG_4, REG_
294 #undef REG_4 macro
[all...]
H A Ds905x-blocks.h119 #define REG_4 S905X_PERIPHS_PIN_MUX_4 macro
266 { .regs = { REG_4, REG_3 }, .bits = { 25, 21 }, },
267 { .regs = { REG_4, 0, REG_3 }, .bits = { 24, 0, 20 }, },
293 #undef REG_4 macro

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