Lines Matching refs:REG_4
119 #define REG_4 S912_PERIPHS_PIN_MUX_4
253 { .regs = { REG_4, REG_3, REG_3, REG_3 }, .bits = { 23, 14, 31, 19 }, },
254 { .regs = { REG_4, REG_3, REG_3, REG_3 }, .bits = { 22, 13, 30, 18 }, },
255 { .regs = { REG_4, 0, REG_3, REG_3 }, .bits = { 21, 0, 29, 17 }, },
256 { .regs = { REG_4, REG_3, REG_3, REG_3 }, .bits = { 20, 12, 28, 16 }, },
257 { .regs = { REG_4, REG_3, REG_3, REG_3 }, .bits = { 19, 11, 27, 15 }, },
258 { .regs = { REG_4, REG_3, REG_3 }, .bits = { 18, 11, 26 }, },
259 { .regs = { REG_4, REG_3, REG_3, REG_4 }, .bits = { 17, 11, 25, 9 }, },
260 { .regs = { REG_4, REG_3, REG_3, REG_4 }, .bits = { 16, 11, 24, 8 }, },
261 { .regs = { REG_4, REG_3, 0, REG_3, REG_4 }, .bits = { 15, 11, 0, 23, 7 }, },
262 { .regs = { REG_4, REG_3, 0, REG_3, REG_4 }, .bits = { 14, 11, 0, 22, 6 }, },
263 { .regs = { REG_4, REG_3, 0, 0, REG_4 }, .bits = { 13, 11, 0, 0, 5 }, },
264 { .regs = { REG_4, REG_3, 0, 0, REG_4 }, .bits = { 12, 11, 0, 0, 4 }, },
265 { .regs = { REG_4, 0, 0, 0, REG_4 }, .bits = { 11, 0, 0, 0, 3 }, },
266 { .regs = { REG_4, 0, 0, 0, REG_4 }, .bits = { 10, 0, 0, 0, 2 }, },
267 { .regs = { REG_4, REG_3 }, .bits = { 25, 21 }, },
268 { .regs = { REG_4, 0, REG_3 }, .bits = { 24, 0, 20 }, },
294 #undef REG_4