/fuchsia/zircon/system/dev/gpio/aml-gxl-gpio/ |
H A D | s905-blocks.h | 130 #define REG_2 S905_PERIPHS_PIN_MUX_2 macro 170 { .regs = { 0, REG_2, 0, 0, REG_2 }, .bits = { 0, 22, 0, 0, 30 }, }, 176 { .regs = { REG_2, REG_3, 0, 0, REG_1 }, .bits = { 19, 2, 0, 0, 0 }, }, 177 { .regs = { REG_2, REG_3, 0, 0, REG_1 }, .bits = { 18, 1, 0, 0, 1 }, }, 178 { .regs = { REG_2, REG_3 }, .bits = { 17, 0 }, }, 179 { .regs = { REG_2, REG_3, 0, 0, REG_1 }, .bits = { 16, 4, 0, 0, 1 }, }, 180 { .regs = { REG_2, REG_3, 0, REG_1 }, .bits = { 16, 5, 0, 12 }, }, 181 { .regs = { REG_2, REG_3, 0, REG_1 }, .bits = { 16, 5, 0, 13 }, }, 182 { .regs = { REG_2, REG_ 324 #undef REG_2 macro [all...] |
H A D | s912-blocks.h | 117 #define REG_2 S912_PERIPHS_PIN_MUX_2 macro 164 { .regs = { REG_3, 0, 0, REG_2, REG_1 }, .bits = { 10, 0, 0, 4, 8 }, }, 165 { .regs = { REG_3, 0, 0, REG_2 }, .bits = { 10, 0, 0, 3 }, }, 166 { .regs = { REG_3, 0, 0, REG_2 }, .bits = { 9, 0, 0, 3 }, }, 167 { .regs = { REG_3, 0, 0, REG_2 }, .bits = { 9, 0, 0, 3 }, }, 168 { .regs = { REG_3, 0, 0, REG_2 }, .bits = { 9, 0, 0, 3 }, }, 169 { .regs = { REG_3, 0, 0, REG_2 }, .bits = { 9, 0, 0, 3 }, }, 170 { .regs = { REG_3, 0, 0, REG_2 }, .bits = { 9, 0, 0, 3 }, }, 171 { .regs = { REG_3, 0, 0, REG_2 }, .bits = { 9, 0, 0, 3 }, }, 172 { .regs = { REG_3, 0, 0, REG_2 }, 292 #undef REG_2 macro [all...] |
H A D | s905x-blocks.h | 117 #define REG_2 S905X_PERIPHS_PIN_MUX_2 macro 188 { .regs = { REG_2, REG_2, REG_1 }, .bits = { 16, 7, 15 }, }, 189 { .regs = { REG_2, REG_2, REG_1 }, .bits = { 15, 6, 14 }, }, 190 { .regs = { REG_2, 0, REG_1 }, .bits = { 14, 0, 13 }, }, 191 { .regs = { REG_2, 0, REG_1 }, .bits = { 13, 0, 12 }, }, 192 { .regs = { REG_2, REG_1, REG_1 }, .bits = { 12, 9, 11 }, }, 193 { .regs = { REG_2, REG_2, REG_ 291 #undef REG_2 macro [all...] |