Lines Matching refs:REG_2
117 #define REG_2 S912_PERIPHS_PIN_MUX_2
164 { .regs = { REG_3, 0, 0, REG_2, REG_1 }, .bits = { 10, 0, 0, 4, 8 }, },
165 { .regs = { REG_3, 0, 0, REG_2 }, .bits = { 10, 0, 0, 3 }, },
166 { .regs = { REG_3, 0, 0, REG_2 }, .bits = { 9, 0, 0, 3 }, },
167 { .regs = { REG_3, 0, 0, REG_2 }, .bits = { 9, 0, 0, 3 }, },
168 { .regs = { REG_3, 0, 0, REG_2 }, .bits = { 9, 0, 0, 3 }, },
169 { .regs = { REG_3, 0, 0, REG_2 }, .bits = { 9, 0, 0, 3 }, },
170 { .regs = { REG_3, 0, 0, REG_2 }, .bits = { 9, 0, 0, 3 }, },
171 { .regs = { REG_3, 0, 0, REG_2 }, .bits = { 9, 0, 0, 3 }, },
172 { .regs = { REG_3, 0, 0, REG_2 }, .bits = { 8, 0, 0, 2 }, },
173 { .regs = { REG_3, 0, 0, REG_2 }, .bits = { 8, 0, 0, 1 }, },
174 { .regs = { REG_3, 0, 0, REG_2 }, .bits = { 7, 0, 0, 0 }, },
186 { .regs = { REG_3, 0, REG_2, REG_1 }, .bits = { 5, 0, 18, 25 }, },
187 { .regs = { REG_3, 0, REG_2, REG_1 }, .bits = { 5, 0, 17, 25 }, },
188 { .regs = { REG_3, REG_1, REG_2, REG_2, REG_1 }, .bits = { 4, 15, 16, 7, 22 }, },
189 { .regs = { REG_3, REG_1, REG_2, REG_2, REG_1 }, .bits = { 3, 14, 15, 6, 21 }, },
190 { .regs = { REG_1, REG_1, REG_2 }, .bits = { 20, 13, 14 }, },
191 { .regs = { REG_1, REG_1, REG_2, 0, REG_1 }, .bits = { 18, 12, 13, 0, 19 }, },
192 { .regs = { REG_2, REG_1, 0, REG_1 }, .bits = { 12, 11, 0, 9 }, },
193 { .regs = { REG_2, REG_1, REG_2 }, .bits = { 11, 10, 5 }, },
292 #undef REG_2