Searched refs:v2i16 (Results 1 - 23 of 23) sorted by relevance

/freebsd-current/contrib/llvm-project/llvm/lib/Target/NVPTX/
H A DNVPTXISelLowering.cpp136 case MVT::v2i16:
219 EltVT = MVT::v2i16;
475 addRegisterClass(MVT::v2i16, &NVPTX::Int32RegsRegClass);
507 setOperationAction(ISD::BUILD_VECTOR, MVT::v2i16, Custom);
508 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v2i16, Custom);
509 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v2i16, Expand);
510 setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v2i16, Expand);
538 MVT::f64, MVT::i1, MVT::i8, MVT::i16, MVT::v2i16, MVT::v4i8,
551 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::v2i16, Expand);
572 setOperationAction(ISD::ROTL, MVT::v2i16, Expan
[all...]
H A DNVPTXUtilities.cpp356 return (VT == MVT::v2f16 || VT == MVT::v2bf16 || VT == MVT::v2i16);
H A DNVPTXISelDAGToDAG.cpp851 case MVT::v2i16:
936 // v2f16/v2bf16/v2i16 is loaded using ld.b32
1289 (EltVT == MVT::i16 && OrigType == MVT::v2i16)) {
/freebsd-current/contrib/llvm-project/llvm/lib/Target/X86/
H A DX86TargetTransformInfo.cpp1568 {TTI::SK_Broadcast, MVT::v2i16, 1}, // pshuflw
1574 {TTI::SK_Reverse, MVT::v2i16, 1}, // pshuflw
1579 {TTI::SK_Splice, MVT::v2i16, 2}, // punpck+psrldq
1584 {TTI::SK_PermuteTwoSrc, MVT::v2i16, 2}, // punpck/pshuflw
1590 {TTI::SK_PermuteSingleSrc, MVT::v2i16, 1}, // pshuflw
2126 { ISD::SIGN_EXTEND, MVT::v2i16, MVT::v2i1, 1 }, member in class:MVT
2145 { ISD::ZERO_EXTEND, MVT::v2i16, MVT::v2i1, 2 }, member in class:MVT
2163 { ISD::TRUNCATE, MVT::v2i1, MVT::v2i16, 2 }, member in class:MVT
2181 { ISD::TRUNCATE, MVT::v2i8, MVT::v2i16, 2 }, // vpmovwb member in class:MVT
2242 { ISD::TRUNCATE, MVT::v2i1, MVT::v2i16,
2373 { ISD::SIGN_EXTEND, MVT::v2i16, MVT::v2i1, 1 }, member in class:MVT
2392 { ISD::ZERO_EXTEND, MVT::v2i16, MVT::v2i1, 2 }, member in class:MVT
2410 { ISD::TRUNCATE, MVT::v2i1, MVT::v2i16, 2 }, member in class:MVT
[all...]
H A DX86ISelLowering.cpp1027 MVT::v2i16, MVT::v4i16, MVT::v2i32 }) {
1151 for (auto VT : {MVT::v2i8, MVT::v4i8, MVT::v8i8, MVT::v2i16, MVT::v4i16}) {
1191 setOperationAction(ISD::STORE, MVT::v2i16, Custom);
1207 setOperationAction(ISD::TRUNCATE, MVT::v2i16, Custom);
1317 setLoadExtAction(LoadExtOp, MVT::v2i64, MVT::v2i16, Legal);
2299 setTruncStoreAction(MVT::v2i64, MVT::v2i16, Legal);
[all...]
/freebsd-current/contrib/llvm-project/llvm/lib/Target/Hexagon/
H A DHexagonISelLowering.cpp638 VT == MVT::v2i16 || VT == MVT::v2i32 || VT == MVT::v4i8 ||
1036 if (OpTy == MVT::v2i16 || OpTy == MVT::v4i8) {
1094 if (OpTy == MVT::v2i16 || OpTy == MVT::v4i8) {
1470 addRegisterClass(MVT::v2i16, &Hexagon::IntRegsRegClass);
1518 setOperationAction(ISD::SETCC, MVT::v2i16, Custom);
1676 setLoadExtAction(ISD::EXTLOAD, MVT::v2i16, MVT::v2i8, Legal);
1677 setLoadExtAction(ISD::ZEXTLOAD, MVT::v2i16, MVT::v2i8, Legal);
1678 setLoadExtAction(ISD::SEXTLOAD, MVT::v2i16, MVT::v2i8, Legal);
1684 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::v2i16, Legal);
1689 MVT::v8i8, MVT::v2i16, MV
[all...]
H A DHexagonISelDAGToDAG.cpp101 case MVT::v2i16:
491 case MVT::v2i16:
H A DHexagonInstrInfo.cpp2724 case MVT::v2i16:
/freebsd-current/contrib/llvm-project/llvm/lib/Target/AArch64/
H A DAArch64TargetTransformInfo.cpp2276 { ISD::TRUNCATE, MVT::v2i16, MVT::v2i64, 1}, // xtn
2342 { ISD::SINT_TO_FP, MVT::v2f32, MVT::v2i16, 3 },
2345 { ISD::UINT_TO_FP, MVT::v2f32, MVT::v2i16, 3 },
2366 { ISD::SINT_TO_FP, MVT::v2f64, MVT::v2i16, 4 },
2369 { ISD::UINT_TO_FP, MVT::v2f64, MVT::v2i16, 4 },
2386 { ISD::FP_TO_SINT, MVT::v2i16, MVT::v2f32, 1 },
2389 { ISD::FP_TO_UINT, MVT::v2i16, MVT::v2f32, 1 },
2410 { ISD::FP_TO_SINT, MVT::v2i16, MVT::v2f64, 2 },
2413 { ISD::FP_TO_UINT, MVT::v2i16, MVT::v2f64, 2 },
2847 {ISD::SDIV, MVT::v8i8, 8}, {ISD::SDIV, MVT::v2i16, member in class:MVT
2850 {ISD::UDIV, MVT::v8i8, 8}, {ISD::UDIV, MVT::v2i16, 5}, member in class:MVT
[all...]
H A DAArch64ISelLowering.cpp932 // load, floating-point truncating stores, or v2i32->v2i16 truncating store.
1212 setTruncStoreAction(MVT::v2i32, MVT::v2i16, Expand);
1260 setOperationAction(ISD::BITCAST, MVT::v2i16, Custom);
1443 setTruncStoreAction(MVT::v2i64, MVT::v2i16, Custom);
1446 setTruncStoreAction(MVT::v2i32, MVT::v2i16, Custom);
4447 case MVT::v2i16:
18127 // (v4i16 (concat_vectors (v2i16 (truncate (v2i64))),
18128 // (v2i16 (truncate (v2i64)))))
24381 if (VT == MVT::v2i16 && SrcVT == MVT::i32) {
[all...]
/freebsd-current/contrib/llvm-project/llvm/lib/Target/AMDGPU/
H A DSIISelLowering.cpp162 addRegisterClass(MVT::v2i16, &AMDGPU::SReg_32RegClass);
238 AddPromotedToType(ISD::BUILD_VECTOR, MVT::v2bf16, MVT::v2i16);
241 setTruncStoreAction(MVT::v2i32, MVT::v2i16, Expand);
252 setTruncStoreAction(MVT::v2i16, MVT::v2i8, Expand);
294 {MVT::v2i1, MVT::v4i1, MVT::v2i8, MVT::v4i8, MVT::v2i16,
435 {MVT::v2i16, MVT::v2f16, MVT::v2bf16, MVT::v2i8, MVT::v4i8,
618 {MVT::v2i16, MVT::v2f16, MVT::v2bf16, MVT::v4i16, MVT::v4f16,
646 setOperationAction(ISD::BSWAP, {MVT::i16, MVT::v2i16}, Legal);
650 setOperationAction(ISD::Constant, {MVT::v2i16, MVT::v2f16}, Legal);
652 setOperationAction(ISD::UNDEF, {MVT::v2i16, MV
[all...]
H A DAMDGPUTargetTransformInfo.cpp688 // Return true if there's a potential benefit from using v2f16/v2i16
743 static const auto ValidSatTys = {MVT::v2i16, MVT::v4i16};
H A DAMDGPUISelDAGToDAG.cpp215 if (VT != MVT::v2i16 && VT != MVT::v2f16)
673 MVT NewVT = Opc == AMDGPUISD::CVT_PKRTZ_F16_F32 ? MVT::v2f16 : MVT::v2i16;
H A DR600ISelLowering.cpp71 setTruncStoreAction(MVT::v2i32, MVT::v2i16, Custom);
136 setOperationAction(ISD::SIGN_EXTEND_INREG, {MVT::v2i16, MVT::v4i16}, Expand);
H A DAMDGPUISelLowering.cpp165 {MVT::v2i8, MVT::v4i8, MVT::v2i16, MVT::v3i16, MVT::v4i16})
292 setTruncStoreAction(MVT::v2i64, MVT::v2i16, Expand);
394 {MVT::v2f16, MVT::v2bf16, MVT::v2i16, MVT::v4f16, MVT::v4bf16,
3963 isOperationLegal(ISD::BUILD_VECTOR, MVT::v2i16)) {
3966 SDValue Vec = DAG.getBuildVector(MVT::v2i16, SL,
/freebsd-current/contrib/llvm-project/llvm/lib/Target/ARM/
H A DARMTargetTransformInfo.cpp663 { ISD::SIGN_EXTEND, MVT::v2i64, MVT::v2i16, 2 },
664 { ISD::ZERO_EXTEND, MVT::v2i64, MVT::v2i16, 2 },
686 { ISD::SINT_TO_FP, MVT::v2f32, MVT::v2i16, 2 },
687 { ISD::UINT_TO_FP, MVT::v2f32, MVT::v2i16, 2 },
718 { ISD::SINT_TO_FP, MVT::v2f64, MVT::v2i16, 3 },
719 { ISD::UINT_TO_FP, MVT::v2f64, MVT::v2i16, 3 },
811 { ISD::SIGN_EXTEND, MVT::v2i64, MVT::v2i16, 10 },
812 { ISD::ZERO_EXTEND, MVT::v2i64, MVT::v2i16, 2 },
H A DARMISelLowering.cpp1006 for (MVT Ty : {MVT::v8i8, MVT::v4i8, MVT::v2i8, MVT::v4i16, MVT::v2i16,
9481 case MVT::v2i16:
/freebsd-current/contrib/llvm-project/llvm/utils/TableGen/
H A DCodeGenTarget.cpp116 case MVT::v2i16: return "MVT::v2i16";
/freebsd-current/contrib/llvm-project/llvm/lib/Target/Mips/
H A DMipsSEISelLowering.cpp85 MVT::SimpleValueType VecTys[2] = {MVT::v2i16, MVT::v4i8};
111 setOperationAction(ISD::MUL, MVT::v2i16, Legal);
867 if ((Ty != MVT::v2i16) && (Ty != MVT::v4i8))
924 if ((Ty != MVT::v2i16) && ((Ty != MVT::v4i8) || !Subtarget.hasDSPR2()))
936 if (((Ty != MVT::v2i16) || !Subtarget.hasDSPR2()) && (Ty != MVT::v4i8))
943 bool IsV216 = (Ty == MVT::v2i16);
963 if ((Ty != MVT::v2i16) && (Ty != MVT::v4i8))
976 if (Ty == MVT::v2i16 || Ty == MVT::v4i8) {
/freebsd-current/contrib/llvm-project/llvm/lib/CodeGen/
H A DValueTypes.cpp287 case MVT::v2i16:
/freebsd-current/contrib/llvm-project/llvm/lib/Target/WebAssembly/
H A DWebAssemblyISelLowering.cpp2499 else if (ResVT == MVT::v2f64 && (InVT == MVT::v2i16 || InVT == MVT::v2i8))
/freebsd-current/contrib/llvm-project/llvm/lib/Target/PowerPC/
H A DPPCISelLowering.cpp901 setOperationAction(ISD::TRUNCATE, MVT::v2i16, Custom);
1110 setOperationAction(ISD::STRICT_UINT_TO_FP, MVT::v2i16, Custom);
1114 setOperationAction(ISD::STRICT_SINT_TO_FP, MVT::v2i16, Custom);
1118 setOperationAction(ISD::UINT_TO_FP, MVT::v2i16, Custom);
1122 setOperationAction(ISD::SINT_TO_FP, MVT::v2i16, Custom);
1314 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::v2i16, Legal);
/freebsd-current/contrib/llvm-project/llvm/lib/Target/AMDGPU/AsmParser/
H A DAMDGPUAsmParser.cpp594 return isVSrcB16() || isLiteralImm(MVT::v2i16);
2067 : (type == MVT::v2i16) ? MVT::f32

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