/freebsd-current/sys/arm/freescale/imx/ |
H A D | imx6_ccm.c | 73 WR4(struct ccm_softc *sc, bus_size_t off, uint32_t val) function 95 WR4(sc, CCM_CCGR0, reg); 100 WR4(sc, CCM_CCGR1, reg); 107 WR4(sc, CCM_CCGR2, reg); 112 WR4(sc, CCM_CCGR3, reg); 117 WR4(sc, CCM_CCGR4, reg); 122 WR4(sc, CCM_CCGR5, reg); 127 WR4(sc, CCM_CCGR6, reg); 179 WR4(sc, CCM_CGPR, reg); 182 WR4(s [all...] |
H A D | imx_epit.c | 140 WR4(struct epit_softc *sc, bus_size_t offset, uint32_t value) function 201 WR4(sc, EPIT_LR, 0xffffffff); 202 WR4(sc, EPIT_CR, sc->ctlreg | EPIT_CR_EN); 232 WR4(sc, EPIT_CR, sc->ctlreg); 233 WR4(sc, EPIT_SR, EPIT_SR_OCIF); 245 WR4(sc, EPIT_LR, ticks); 259 WR4(sc, EPIT_CR, sc->ctlreg); 284 WR4(sc, EPIT_CR, sc->ctlreg); 448 WR4(sc, EPIT_CR, 0);
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/freebsd-current/sys/arm/nvidia/drm2/ |
H A D | tegra_dc.c | 55 #define WR4(_sc, _r, _v) bus_write_4((_sc)->mem_res, 4 * (_r), (_v)) macro 423 WR4(sc, DC_CMD_DISPLAY_WINDOW_HEADER, val); 426 WR4(sc, DC_WIN_POSITION, WIN_POSITION(win->dst_x, win->dst_y)); 427 WR4(sc, DC_WIN_SIZE, WIN_SIZE(win->dst_w, win->dst_h)); 428 WR4(sc, DC_WIN_PRESCALED_SIZE, WIN_PRESCALED_SIZE(h_size, v_size)); 431 WR4(sc, DC_WIN_DDA_INCREMENT, 433 WR4(sc, DC_WIN_H_INITIAL_DDA, h_init_dda); 434 WR4(sc, DC_WIN_V_INITIAL_DDA, v_init_dda); 437 WR4(sc, DC_WINBUF_START_ADDR, win->base[0]); 439 WR4(s [all...] |
H A D | tegra_hdmi.c | 58 #define WR4(_sc, _r, _v) bus_write_4((_sc)->mem_res, 4 * (_r), (_v)) macro 354 WR4(sc, HDMI_NV_PDISP_HDMI_AVI_INFOFRAME_HEADER, 356 WR4(sc, HDMI_NV_PDISP_HDMI_AVI_INFOFRAME_SUBPACK0_LOW, 358 WR4(sc, HDMI_NV_PDISP_HDMI_AVI_INFOFRAME_SUBPACK0_HIGH, 360 WR4(sc, HDMI_NV_PDISP_HDMI_AVI_INFOFRAME_SUBPACK1_LOW, 362 WR4(sc, HDMI_NV_PDISP_HDMI_AVI_INFOFRAME_SUBPACK1_HIGH, 365 WR4(sc, HDMI_NV_PDISP_HDMI_AVI_INFOFRAME_CTRL, 385 WR4(sc, HDMI_NV_PDISP_HDMI_AUDIO_INFOFRAME_HEADER, 387 WR4(sc, HDMI_NV_PDISP_HDMI_AUDIO_INFOFRAME_SUBPACK0_LOW, 389 WR4(s [all...] |
/freebsd-current/sys/dev/ffec/ |
H A D | if_ffec.c | 231 WR4(struct ffec_softc *sc, bus_size_t off, uint32_t val) function 324 WR4(sc, FEC_IER_REG, FEC_IER_MII); 326 WR4(sc, FEC_MMFR_REG, FEC_MMFR_OP_READ | 348 WR4(sc, FEC_IER_REG, FEC_IER_MII); 350 WR4(sc, FEC_MMFR_REG, FEC_MMFR_OP_WRITE | 436 WR4(sc, FEC_RCR_REG, rcr); 437 WR4(sc, FEC_TCR_REG, tcr); 438 WR4(sc, FEC_ECR_REG, ecr); 490 WR4(sc, FEC_MIBC_REG, mibc | FEC_MIBC_CLEAR); 491 WR4(s [all...] |
/freebsd-current/sys/arm/xilinx/ |
H A D | zy7_spi.c | 93 #define WR4(sc, off, val) (bus_write_4((sc)->mem_res, (off), (val))) macro 163 WR4(sc, ZY7_SPI_TX_DATA_REG, (uint32_t)byte); 206 WR4(sc, ZY7_SPI_INTR_DIS_REG, 236 WR4(sc, ZY7_SPI_INTR_STAT_REG, 246 WR4(sc, ZY7_SPI_INTR_DIS_REG, 256 WR4(sc, ZY7_SPI_INTR_STAT_REG, 270 WR4(sc, ZY7_SPI_INTR_DIS_REG, 272 WR4(sc, ZY7_SPI_INTR_EN_REG, 284 WR4(sc, ZY7_SPI_CONFIG_REG, sc->cfg_reg_shadow); 316 WR4(s [all...] |
H A D | uart_dev_cdnc.c | 56 #define WR4(bas, reg, value) \ macro 208 WR4(bas, CDNC_UART_BAUDDIV_REG, best_bauddiv); 209 WR4(bas, CDNC_UART_BAUDGEN_REG, best_baudgen); 256 WR4(bas, CDNC_UART_MODE_REG, mode_reg_value); 269 WR4(bas, CDNC_UART_CTRL_REG, 273 WR4(bas, CDNC_UART_IDIS_REG, CDNC_UART_INT_ALL); 274 WR4(bas, CDNC_UART_ISTAT_REG, CDNC_UART_INT_ALL); 277 WR4(bas, CDNC_UART_MODEM_STAT_REG, 282 WR4(bas, CDNC_UART_RX_WATER_REG, UART_FIFO_SIZE/2); 283 WR4(ba [all...] |
H A D | zy7_qspi.c | 106 #define WR4(sc, off, val) (bus_write_4((sc)->mem_res, (off), (val))) macro 251 WR4(sc, ZY7_QSPI_TXD1_REG, data); 254 WR4(sc, ZY7_QSPI_TXD2_REG, data); 257 WR4(sc, ZY7_QSPI_TXD3_REG, data); 260 WR4(sc, ZY7_QSPI_TXD0_REG, data); 321 WR4(sc, ZY7_QSPI_INTR_DIS_REG, 351 WR4(sc, ZY7_QSPI_INTR_STAT_REG, 361 WR4(sc, ZY7_QSPI_INTR_DIS_REG, 375 WR4(sc, ZY7_QSPI_INTR_STAT_REG, 390 WR4(s [all...] |
H A D | zy7_slcr.c | 74 #define WR4(sc, off, val) (bus_write_4((sc)->mem_res, (off), (val))) macro 114 WR4(sc, ZY7_SLCR_UNLOCK, ZY7_SLCR_UNLOCK_MAGIC); 122 WR4(sc, ZY7_SLCR_LOCK, ZY7_SLCR_LOCK_MAGIC); 136 WR4(sc, ZY7_SLCR_REBOOT_STAT, 140 WR4(sc, ZY7_SLCR_PSS_RST_CTRL, ZY7_SLCR_PSS_RST_CTRL_SOFT_RESET); 163 WR4(sc, ZY7_SLCR_FPGA_RST_CTRL, ZY7_SLCR_FPGA_RST_CTRL_RST_ALL); 166 WR4(sc, ZY7_SLCR_LVL_SHFTR_EN, 0); 194 WR4(sc, ZY7_SLCR_LVL_SHFTR_EN, ZY7_SLCR_LVL_SHFTR_EN_ALL); 197 WR4(sc, ZY7_SLCR_FPGA_RST_CTRL, 0); 239 WR4(s [all...] |
H A D | zy7_devcfg.c | 97 #define WR4(sc, off, val) (bus_write_4((sc)->mem_res, (off), (val))) macro 402 WR4(sc, ZY7_DEVCFG_CTRL, 415 WR4(sc, ZY7_DEVCFG_MCTRL, RD4(sc, ZY7_DEVCFG_MCTRL) & 431 WR4(sc, ZY7_DEVCFG_INT_STATUS, ZY7_DEVCFG_INT_ALL); 432 WR4(sc, ZY7_DEVCFG_INT_MASK, ~ZY7_DEVCFG_INT_PCFG_INIT_PE); 436 WR4(sc, ZY7_DEVCFG_CTRL, devcfg_ctl); 445 WR4(sc, ZY7_DEVCFG_INT_MASK, ~0); 456 WR4(sc, ZY7_DEVCFG_CTRL, devcfg_ctl); 468 WR4(sc, ZY7_DEVCFG_INT_STATUS, ZY7_DEVCFG_INT_ALL); 469 WR4(s [all...] |
/freebsd-current/sys/arm64/broadcom/genet/ |
H A D | if_genet.c | 81 #define WR4(sc, reg, val) bus_write_4((sc)->res[_RES_MAC], (reg), (val)) macro 463 WR4(sc, GENET_SYS_RBUF_FLUSH_CTRL, val); 467 WR4(sc, GENET_SYS_RBUF_FLUSH_CTRL, val); 470 WR4(sc, GENET_SYS_RBUF_FLUSH_CTRL, 0); 473 WR4(sc, GENET_UMAC_CMD, 0); 474 WR4(sc, GENET_UMAC_CMD, 477 WR4(sc, GENET_UMAC_CMD, 0); 479 WR4(sc, GENET_UMAC_MIB_CTRL, GENET_UMAC_MIB_RESET_RUNT | 481 WR4(sc, GENET_UMAC_MIB_CTRL, 0); 489 WR4(s [all...] |
/freebsd-current/sys/arm64/nvidia/tegra210/ |
H A D | tegra210_xusbpadctl.c | 324 #define WR4(_sc, _r, _v) bus_write_4((_sc)->mem_res, (_r), (_v)) macro 573 WR4(sc, XUSB_PADCTL_UPHY_PLL_P0_CTL2, reg); 578 WR4(sc, XUSB_PADCTL_UPHY_PLL_P0_CTL5, reg); 582 WR4(sc, XUSB_PADCTL_UPHY_PLL_P0_CTL1, reg); 586 WR4(sc, XUSB_PADCTL_UPHY_PLL_P0_CTL2, reg); 590 WR4(sc, XUSB_PADCTL_UPHY_PLL_P0_CTL8, reg); 601 WR4(sc, XUSB_PADCTL_UPHY_PLL_P0_CTL4, reg); 607 WR4(sc, XUSB_PADCTL_UPHY_PLL_P0_CTL1, reg); 611 WR4(sc, XUSB_PADCTL_UPHY_PLL_P0_CTL1, reg); 615 WR4(s [all...] |
H A D | tegra210_clk_pll.c | 607 WR4(sc, sc->base_reg, reg); 620 WR4(sc, sc->base_reg, reg); 760 WR4(sc, sc->base_reg, reg); 766 WR4(sc, PLLE_AUX, reg); 776 WR4(sc, sc->misc_reg, reg); 781 WR4(sc, PLLE_SS_CNTL, reg); 785 WR4(sc, sc->base_reg, reg); 802 WR4(sc, PLLE_SS_CNTL, reg); 805 WR4(sc, PLLE_SS_CNTL, reg); 809 WR4(s [all...] |
H A D | tegra210_pmc.c | 188 WR4(struct tegra210_pmc_softc *sc, bus_size_t r, uint32_t v) function 243 WR4(sc, PMC_PWRGATE_TOGGLE, 270 WR4(sc, PMC_GPU_RG_CNTRL, 0); 284 WR4(sc, PMC_REMOVE_CLAMPING_CMD, PMC_REMOVE_CLAMPING_CMD_PARTID(swid)); 506 WR4(sc, PMC_SCRATCH0, 0xDEADBEEF); 511 WR4(sc, PMC_SCRATCH0, 0xBADC0DE); 516 WR4(sc, PMC_SCRATCH0, orig); 579 WR4(sc, PMC_CNTRL, reg); 587 WR4(sc, PMC_CNTRL, reg); 592 WR4(s [all...] |
/freebsd-current/sys/dev/hwpmc/ |
H A D | pmu_dmc620.c | 70 #define WR4(sc, r, v) bus_write_4((sc)->sc_res[0], (r), (v)) macro 71 #define MD4(sc, r, c, s) WR4((sc), (r), (RD4((sc), (r)) & ~(c)) | (s)) 99 WR4(sc, DMC620_REG(cntr, reg), val); 155 WR4(sc, DMC620_OVERFLOW_STATUS_CLKDIV2, 0); 156 WR4(sc, DMC620_OVERFLOW_STATUS_CLK, 0); 224 WR4(sc, DMC620_REG(i, DMC620_COUNTER_CONTROL), 234 WR4(sc, DMC620_OVERFLOW_STATUS_CLKDIV2, 0); 242 WR4(sc, DMC620_OVERFLOW_STATUS_CLK, 0); 247 WR4(sc, DMC620_REG(i, DMC620_COUNTER_CONTROL),
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/freebsd-current/sys/arm64/rockchip/ |
H A D | rk_tsadc.c | 100 #define WR4(_sc, _r, _v) bus_write_4((_sc)->mem_res, (_r), (_v)) macro 484 WR4(sc, TSADC_INT_EN, val); 488 WR4(sc, TSADC_COMP_SHUT(sensor->channel), val); 491 WR4(sc, TSADC_AUTO_CON, val); 495 WR4(sc, TSADC_COMP_INT(sensor->channel), val); 498 WR4(sc, TSADC_INT_EN, val); 514 WR4(sc, TSADC_AUTO_CON, val); 519 WR4(sc, TSADC_AUTO_PERIOD, 250); /* 250 ms */ 520 WR4(sc, TSADC_AUTO_PERIOD_HT, 50); /* 50 ms */ 521 WR4(s [all...] |
/freebsd-current/sys/dev/eqos/ |
H A D | if_eqos.c | 98 #define WR4(sc, o, v) bus_write_4(sc->res[EQOS_RES_MEM], (o), (v)) macro 121 WR4(sc, GMAC_MAC_MDIO_ADDRESS, addr); 148 WR4(sc, GMAC_MAC_MDIO_DATA, val); 154 WR4(sc, GMAC_MAC_MDIO_ADDRESS, addr); 217 WR4(sc, GMAC_MAC_CONFIGURATION, reg); 221 WR4(sc, GMAC_MAC_1US_TIC_COUNTER, (sc->csr_clock / 1000000) - 1); 372 WR4(sc, GMAC_DMA_CHAN0_INTR_ENABLE, 382 WR4(sc, GMAC_DMA_CHAN0_INTR_ENABLE, 0); 439 WR4(sc, GMAC_MAC_ADDRESS0_HIGH, val); 442 WR4(s [all...] |
/freebsd-current/sys/arm/broadcom/bcm2835/ |
H A D | bcm2835_sdhost.c | 243 WR4(struct bcm_sdhost_softc *sc, bus_size_t off, uint32_t val) function 279 WR4(sc, off & ~3, val32); 290 WR4(sc, off & ~3, val32); 346 WR4(sc, HC_POWER, 0); 348 WR4(sc, HC_COMMAND, 0); 349 WR4(sc, HC_ARGUMENT, 0); 350 WR4(sc, HC_TIMEOUTCOUNTER, HC_TIMEOUT_DEFAULT); 351 WR4(sc, HC_CLOCKDIVISOR, 0); 352 WR4(sc, HC_HOSTSTATUS, HC_HSTST_RESET); 353 WR4(s [all...] |
/freebsd-current/sys/arm/nvidia/tegra124/ |
H A D | tegra124_clk_pll.c | 421 WR4(sc, sc->base_reg, reg); 434 WR4(sc, sc->base_reg, reg); 568 WR4(sc, sc->base_reg, reg); 573 WR4(sc, PLLE_AUX, reg); 583 WR4(sc, sc->misc_reg, reg); 588 WR4(sc, PLLE_SS_CNTL, reg); 594 WR4(sc, sc->base_reg, reg); 607 WR4(sc, PLLE_SS_CNTL, reg); 610 WR4(sc, PLLE_SS_CNTL, reg); 614 WR4(s [all...] |
H A D | tegra124_xusbpadctl.c | 170 #define WR4(_sc, _r, _v) bus_write_4((_sc)->mem_res, (_r), (_v)) macro 375 WR4(sc, XUSB_PADCTL_SS_PORT_MAP, reg); 384 WR4(sc, XUSB_PADCTL_IOPHY_USB3_PAD_CTL2(port->idx), reg); 386 WR4(sc, XUSB_PADCTL_IOPHY_USB3_PAD_CTL4(port->idx), 391 WR4(sc, XUSB_PADCTL_ELPG_PROGRAM, reg); 396 WR4(sc, XUSB_PADCTL_ELPG_PROGRAM, reg); 401 WR4(sc, XUSB_PADCTL_ELPG_PROGRAM, reg); 415 WR4(sc, XUSB_PADCTL_IOPHY_PLL_P0_CTL1, reg); 422 WR4(sc, XUSB_PADCTL_IOPHY_PLL_P0_CTL2, reg); 427 WR4(s [all...] |
/freebsd-current/sys/arm64/qoriq/ |
H A D | qoriq_therm.c | 196 WR4(struct qoriq_therm_softc *sc, bus_size_t addr, uint32_t val) function 315 WR4(sc, TMU_TTRCR(i), ranges[i]); 326 WR4(sc, TMU_TTCFGR, calibs[i]); 327 WR4(sc, TMU_TSCFGR, calibs[i + 1]); 423 WR4(sc, TMU_TMR, 0); 427 WR4(sc, TMU_TIER, 0); 431 WR4(sc, TMUV1_TMTMIR, 0x0F); 433 WR4(sc, TMUV2_TMTMIR, 0x0F); /* disable */ 435 WR4(sc, TMUV2_TEUMR(0), 0x51009c00); 437 WR4(s [all...] |
/freebsd-current/sys/arm/mv/ |
H A D | mv_thermal.c | 123 #define WR4(sc, reg, val) \ macro 165 WR4(sc, CONTROL0, reg); 181 WR4(sc, CONTROL0, reg); 187 WR4(sc, CONTROL0, reg); 228 WR4(sc, CONTROL0, reg); 244 WR4(sc, CONTROL1, reg); 249 WR4(sc, CONTROL0, reg);
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H A D | mv_cp110_icu.c | 100 #define WR4(sc, reg, val) bus_write_4((sc)->res, (reg), (val)) macro 161 WR4(sc, ICU_INT_CFG(i), 0); 249 WR4(sc, ICU_SETSPI_NSR_AL, addr & UINT32_MAX); 250 WR4(sc, ICU_SETSPI_NSR_AH, (addr >> 32) & UINT32_MAX); 252 WR4(sc, ICU_CLRSPI_NSR_AL, addr & UINT32_MAX); 253 WR4(sc, ICU_CLRSPI_NSR_AH, (addr >> 32) & UINT32_MAX); 256 WR4(sc, ICU_SETSPI_SEI_AL, addr & UINT32_MAX); 257 WR4(sc, ICU_SETSPI_SEI_AH, (addr >> 32) & UINT32_MAX); 319 WR4(sc, ICU_INT_CFG(irq_no), vector); 329 WR4(s [all...] |
/freebsd-current/sys/arm/nvidia/ |
H A D | tegra_rtc.c | 75 #define WR4(_sc, _r, _v) bus_write_4((_sc)->mem_res, (_r), (_v)) macro 154 WR4(sc, RTC_SECONDS, tv.tv_sec); 169 WR4(sc, RTC_INTR_STATUS, status); 229 WR4(sc, RTC_SECONDS_ALARM0, 0); 230 WR4(sc, RTC_SECONDS_ALARM1, 0); 231 WR4(sc, RTC_INTR_STATUS, 0xFFFFFFFF); 232 WR4(sc, RTC_INTR_MASK, 0);
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/freebsd-current/sys/dev/sdhci/ |
H A D | sdhci_fsl_fdt.c | 57 #define WR4 (sc->write) macro 325 WR4(sc, SDHCI_CLOCK_CONTROL, val32 & ~SDHCI_FSL_CLK_SDCLKEN); 372 WR4(sc, SDHCI_CLOCK_CONTROL, val32); 492 WR4(sc, SDHCI_FSL_PROT_CTRL, val32); 500 WR4(sc, off & ~3, val32); 529 WR4(sc, SDHCI_TRANSFER_MODE, sc->cmd_and_mode); 543 WR4(sc, off & ~3, val32); 572 WR4(sc, off, val); 723 WR4(sc, SDHCI_FSL_PROT_CTRL, val); 747 WR4(s [all...] |