1/*-
2 * SPDX-License-Identifier: BSD-2-Clause
3 *
4 * Copyright (c) 2021 Ampere Computing LLC
5 *
6 * Redistribution and use in source and binary forms, with or without
7 * modification, are permitted provided that the following conditions
8 * are met:
9 * 1. Redistributions of source code must retain the above copyright
10 *    notice, this list of conditions and the following disclaimer.
11 * 2. Redistributions in binary form must reproduce the above copyright
12 *    notice, this list of conditions and the following disclaimer in the
13 *    documentation and/or other materials provided with the distribution.
14 *
15 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
16 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
17 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
18 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
19 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
20 * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
21 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
22 * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
23 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
24 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
25 * SUCH DAMAGE.
26 */
27
28#include <sys/cdefs.h>
29#include "opt_hwpmc_hooks.h"
30#include "opt_acpi.h"
31
32#include <sys/param.h>
33#include <sys/bus.h>
34#include <sys/module.h>
35#include <sys/rman.h>
36#include <sys/pmc.h>
37#include <sys/pmckern.h>
38
39#include <machine/bus.h>
40#include <machine/cpu.h>
41
42#include <contrib/dev/acpica/include/acpi.h>
43#include <dev/acpica/acpivar.h>
44
45#include <dev/hwpmc/pmu_dmc620_reg.h>
46
47static char *pmu_dmc620_ids[] = {
48	"ARMHD620",
49	NULL
50};
51
52static struct resource_spec pmu_dmc620_res_spec[] = {
53	{ SYS_RES_MEMORY,	0,	RF_ACTIVE },
54	{ SYS_RES_IRQ,		0,	RF_ACTIVE | RF_SHAREABLE },
55	{ -1, 0 }
56};
57
58struct pmu_dmc620_softc {
59	device_t	sc_dev;
60	int		sc_unit;
61	int		sc_domain;
62	struct resource *sc_res[2];
63	void		*sc_ih;
64	uint32_t	sc_clkdiv2_conters_hi[DMC620_CLKDIV2_COUNTERS_N];
65	uint32_t	sc_clk_conters_hi[DMC620_CLK_COUNTERS_N];
66	uint32_t	sc_saved_control[DMC620_COUNTERS_N];
67};
68
69#define	RD4(sc, r)		bus_read_4((sc)->sc_res[0], (r))
70#define	WR4(sc, r, v)		bus_write_4((sc)->sc_res[0], (r), (v))
71#define	MD4(sc, r, c, s)	WR4((sc), (r), (RD4((sc), (r)) & ~(c)) | (s))
72
73#define	CD2MD4(sc, u, r, c, s)	MD4((sc), DMC620_CLKDIV2_REG((u), (r)), (c), (s))
74#define	CMD4(sc, u, r, c, s)	MD4((sc), DMC620_CLK_REG((u), (r)), (c), (s))
75
76static int pmu_dmc620_counter_overflow_intr(void *arg);
77
78uint32_t
79pmu_dmc620_rd4(void *arg, u_int cntr, off_t reg)
80{
81	struct pmu_dmc620_softc *sc;
82	uint32_t val;
83
84	sc = (struct pmu_dmc620_softc *)arg;
85	KASSERT(cntr < DMC620_COUNTERS_N, ("Wrong counter unit %d", cntr));
86
87	val = RD4(sc, DMC620_REG(cntr, reg));
88	return (val);
89}
90
91void
92pmu_dmc620_wr4(void *arg, u_int cntr, off_t reg, uint32_t val)
93{
94	struct pmu_dmc620_softc *sc;
95
96	sc = (struct pmu_dmc620_softc *)arg;
97	KASSERT(cntr < DMC620_COUNTERS_N, ("Wrong counter unit %d", cntr));
98
99	WR4(sc, DMC620_REG(cntr, reg), val);
100}
101
102static int
103pmu_dmc620_acpi_probe(device_t dev)
104{
105	int err;
106
107	err = ACPI_ID_PROBE(device_get_parent(dev), dev, pmu_dmc620_ids, NULL);
108	if (err <= 0)
109		device_set_desc(dev, "ARM DMC-620 Memory Controller PMU");
110
111	return (err);
112}
113
114static int
115pmu_dmc620_acpi_attach(device_t dev)
116{
117	struct pmu_dmc620_softc *sc;
118	int domain, i, u;
119	const char *dname;
120
121	dname = device_get_name(dev);
122	sc = device_get_softc(dev);
123	sc->sc_dev = dev;
124	u = device_get_unit(dev);
125	sc->sc_unit = u;
126
127	/*
128	 * Ampere Altra support NUMA emulation, but DMC-620 PMU units have no
129	 * mapping. Emulate this with kenv/hints.
130	 * Format "hint.pmu_dmc620.3.domain=1".
131	 */
132	if ((resource_int_value(dname, u, "domain", &domain) == 0 ||
133	    bus_get_domain(dev, &domain) == 0) && domain < MAXMEMDOM) {
134		sc->sc_domain = domain;
135	}
136	device_printf(dev, "domain=%d\n", domain);
137
138	i = bus_alloc_resources(dev, pmu_dmc620_res_spec, sc->sc_res);
139	if (i != 0) {
140		device_printf(dev, "cannot allocate resources for device (%d)\n",
141		    i);
142		return (i);
143	}
144	/* Disable counter before enable interrupt. */
145	for (i = 0; i < DMC620_CLKDIV2_COUNTERS_N; i++) {
146		CD2MD4(sc, i, DMC620_COUNTER_CONTROL,
147		    DMC620_COUNTER_CONTROL_ENABLE, 0);
148	}
149	for (i = 0; i < DMC620_CLK_COUNTERS_N; i++) {
150		CMD4(sc, i, DMC620_COUNTER_CONTROL,
151		    DMC620_COUNTER_CONTROL_ENABLE, 0);
152	}
153
154	/* Clear intr status. */
155	WR4(sc, DMC620_OVERFLOW_STATUS_CLKDIV2, 0);
156	WR4(sc, DMC620_OVERFLOW_STATUS_CLK, 0);
157
158	if (sc->sc_res[1] != NULL && bus_setup_intr(dev, sc->sc_res[1],
159	    INTR_TYPE_MISC | INTR_MPSAFE, pmu_dmc620_counter_overflow_intr,
160	    NULL, sc, &sc->sc_ih)) {
161		bus_release_resources(dev, pmu_dmc620_res_spec, sc->sc_res);
162		device_printf(dev, "cannot setup interrupt handler\n");
163		return (ENXIO);
164	}
165	dmc620_pmc_register(u, sc, domain);
166	return (0);
167}
168
169static int
170pmu_dmc620_acpi_detach(device_t dev)
171{
172	struct pmu_dmc620_softc *sc;
173
174	sc = device_get_softc(dev);
175	dmc620_pmc_unregister(device_get_unit(dev));
176	if (sc->sc_res[1] != NULL) {
177		bus_teardown_intr(dev, sc->sc_res[1], sc->sc_ih);
178	}
179	bus_release_resources(dev, pmu_dmc620_res_spec, sc->sc_res);
180
181	return (0);
182}
183
184static void
185pmu_dmc620_clkdiv2_overflow(struct trapframe *tf, struct pmu_dmc620_softc *sc,
186    u_int i)
187{
188
189	atomic_add_32(&sc->sc_clkdiv2_conters_hi[i], 1);
190	/* Call dmc620 handler directly, because hook busy by arm64_intr. */
191	dmc620_intr(tf, PMC_CLASS_DMC620_PMU_CD2, sc->sc_unit, i);
192}
193
194static void
195pmu_dmc620_clk_overflow(struct trapframe *tf, struct pmu_dmc620_softc *sc,
196    u_int i)
197{
198
199	atomic_add_32(&sc->sc_clk_conters_hi[i], 1);
200	/* Call dmc620 handler directly, because hook busy by arm64_intr. */
201	dmc620_intr(tf, PMC_CLASS_DMC620_PMU_C, sc->sc_unit, i);
202
203}
204
205static int
206pmu_dmc620_counter_overflow_intr(void *arg)
207{
208	uint32_t clkdiv2_stat, clk_stat;
209	struct pmu_dmc620_softc *sc;
210	struct trapframe *tf;
211	u_int i;
212
213	tf = PCPU_GET(curthread)->td_intr_frame;
214	sc = (struct pmu_dmc620_softc *) arg;
215	clkdiv2_stat = RD4(sc, DMC620_OVERFLOW_STATUS_CLKDIV2);
216	clk_stat = RD4(sc, DMC620_OVERFLOW_STATUS_CLK);
217
218	if ((clkdiv2_stat == 0) && (clk_stat == 0))
219		return (FILTER_STRAY);
220	/* Stop and save states of all counters. */
221	for (i = 0; i < DMC620_COUNTERS_N; i++) {
222		sc->sc_saved_control[i] = RD4(sc, DMC620_REG(i,
223		    DMC620_COUNTER_CONTROL));
224		WR4(sc, DMC620_REG(i, DMC620_COUNTER_CONTROL),
225		    sc->sc_saved_control[i] & ~DMC620_COUNTER_CONTROL_ENABLE);
226	}
227
228	if (clkdiv2_stat != 0) {
229		for (i = 0; i < DMC620_CLKDIV2_COUNTERS_N; i++) {
230			if ((clkdiv2_stat & (1 << i)) == 0)
231				continue;
232			pmu_dmc620_clkdiv2_overflow(tf, sc, i);
233		}
234		WR4(sc, DMC620_OVERFLOW_STATUS_CLKDIV2, 0);
235	}
236	if (clk_stat != 0) {
237		for (i = 0; i < DMC620_CLK_COUNTERS_N; i++) {
238			if ((clk_stat & (1 << i)) == 0)
239				continue;
240			pmu_dmc620_clk_overflow(tf, sc, i);
241		}
242		WR4(sc, DMC620_OVERFLOW_STATUS_CLK, 0);
243	}
244
245	/* Restore states of all counters. */
246	for (i = 0; i < DMC620_COUNTERS_N; i++) {
247		WR4(sc, DMC620_REG(i, DMC620_COUNTER_CONTROL),
248		    sc->sc_saved_control[i]);
249	}
250
251	return (FILTER_HANDLED);
252}
253
254static device_method_t pmu_dmc620_acpi_methods[] = {
255	/* Device interface */
256	DEVMETHOD(device_probe,			pmu_dmc620_acpi_probe),
257	DEVMETHOD(device_attach,		pmu_dmc620_acpi_attach),
258	DEVMETHOD(device_detach,		pmu_dmc620_acpi_detach),
259
260	/* End */
261	DEVMETHOD_END
262};
263
264static driver_t pmu_dmc620_acpi_driver = {
265	"pmu_dmc620",
266	pmu_dmc620_acpi_methods,
267	sizeof(struct pmu_dmc620_softc),
268};
269
270DRIVER_MODULE(pmu_dmc620, acpi, pmu_dmc620_acpi_driver, 0, 0);
271/* Reverse dependency. hwpmc needs DMC-620 on ARM64. */
272MODULE_DEPEND(pmc, pmu_dmc620, 1, 1, 1);
273MODULE_VERSION(pmu_dmc620, 1);
274