Searched refs:Src1 (Results 1 - 25 of 62) sorted by relevance

123

/freebsd-current/contrib/llvm-project/llvm/lib/Target/AMDGPU/
H A DAMDGPUCombinerHelper.h31 Register Src1, Register Src2);
33 Register Src1, Register Src2);
H A DR600ExpandSpecialInstrs.cpp149 Register Src1 = local
153 (void) Src1;
155 (TRI.getEncodingValue(Src1) & 0xff) < 127)
156 assert(TRI.getHWRegChan(Src0) == TRI.getHWRegChan(Src1));
200 unsigned Src1 = 0; local
206 Src1 = MI.getOperand(Src1Idx).getReg();
212 Src1 = TRI.getSubReg(Src1, SubRegIndex);
217 Src1 = TRI.getSubReg(Src0, SubRegIndex1);
252 TII->buildDefaultInstruction(MBB, I, Opcode, DstReg, Src0, Src1);
[all...]
H A DSIShrinkInstructions.cpp227 MachineOperand &Src1 = MI.getOperand(1);
228 if (!Src1.isImm())
239 if (isKImmOrKUImmOperand(Src1, HasUImm)) {
243 Src1.setImm(SignExtend32(Src1.getImm(), 32));
254 if ((TII->sopkIsZext(SOPKOpc) && isKUImmOperand(Src1)) ||
255 (!TII->sopkIsZext(SOPKOpc) && isKImmOperand(Src1))) {
257 Src1.setImm(SignExtend64(Src1.getImm(), 32));
399 MachineOperand &Src1 local
493 MachineOperand *Src1 = &MI.getOperand(2); local
826 MachineOperand *Src1 = &MI.getOperand(2); local
[all...]
H A DAMDGPUInstCombineIntrinsic.cpp45 static APFloat fmed3AMDGCN(const APFloat &Src0, const APFloat &Src1, argument
47 APFloat Max3 = maxnum(maxnum(Src0, Src1), Src2);
52 return maxnum(Src1, Src2);
54 APFloat::cmpResult Cmp1 = Max3.compare(Src1);
59 return maxnum(Src0, Src1);
606 Value *Src1 = II.getArgOperand(1);
607 const ConstantInt *CMask = dyn_cast<ConstantInt>(Src1);
613 II.setArgOperand(1, ConstantInt::get(Src1->getType(),
619 if (isa<PoisonValue>(Src0) || isa<PoisonValue>(Src1))
623 if (IC.getSimplifyQuery().isUndefValue(Src1))
[all...]
H A DSIOptimizeExecMasking.cpp143 const MachineOperand &Src1 = MI.getOperand(1); local
144 if (Src1.isReg() && Src1.getReg() == AMDGPU::EXEC)
159 const MachineOperand &Src1 = MI.getOperand(1); local
160 if (Src1.isReg() && Src1.getReg() == AMDGPU::EXEC_LO)
537 MachineOperand &Src1 = SaveExecInst->getOperand(2); local
542 OtherOp = &Src1;
543 } else if (Src1.isReg() && Src1
584 MachineOperand *Src1 = TII->getNamedOperand(VCmp, AMDGPU::OpName::src1); local
[all...]
H A DAMDGPURegBankCombiner.cpp317 MachineInstr *Src1 = getDefIgnoringCopies(MI.getOperand(2).getReg(), MRI); local
320 if (isFCst(Src0) && !isFCst(Src1))
321 std::swap(Src0, Src1);
322 if (isFCst(Src1) && !isFCst(Src2))
323 std::swap(Src1, Src2);
324 if (isFCst(Src0) && !isFCst(Src1))
325 std::swap(Src0, Src1);
326 if (!isClampZeroToOne(Src1, Src2))
H A DSIPeepholeSDWA.cpp547 MachineOperand *Src1 = TII->getNamedOperand(MI, AMDGPU::OpName::src1); local
549 if (!Src1->isReg() || Src1->getReg().isPhysical() ||
556 Dst, Src1, *Imm == 16 ? WORD_1 : BYTE_3, UNUSED_PAD);
559 Src1, Dst, *Imm == 16 ? WORD_1 : BYTE_3, false, false,
585 MachineOperand *Src1 = TII->getNamedOperand(MI, AMDGPU::OpName::src1); local
588 if (!Src1->isReg() || Src1->getReg().isPhysical() ||
594 return std::make_unique<SDWADstOperand>(Dst, Src1, BYTE_1, UNUSED_PAD);
597 Src1, Ds
620 MachineOperand *Src1 = TII->getNamedOperand(MI, AMDGPU::OpName::src1); local
667 MachineOperand *Src1 = TII->getNamedOperand(MI, AMDGPU::OpName::src1); local
1025 MachineOperand *Src1 = TII->getNamedOperand(MI, AMDGPU::OpName::src1); local
[all...]
H A DGCNDPPCombine.cpp313 auto *Src1 = TII->getNamedOperand(OrigMI, AMDGPU::OpName::src1); local
314 if (Src1) {
322 "Src0 and Src1 operands should have the same size");
325 if (!TII->isOperandLegal(*DPPInst.getInstr(), OpNum, Src1)) {
330 DPPInst.add(*Src1);
486 auto *Src1 = TII->getNamedOperand(OrigMI, AMDGPU::OpName::src1); local
487 if (!Src1 || !Src1->isReg()) {
495 CombOldVGPR = getRegSubRegPair(*Src1);
681 auto *Src1 local
[all...]
H A DAMDGPUCombinerHelper.cpp420 Register Src1,
427 return isFPExtFromF16OrConst(MRI, Src0) && isFPExtFromF16OrConst(MRI, Src1) &&
433 Register Src1,
440 Src1 = Builder.buildFPTrunc(LLT::scalar(16), Src1).getReg(0);
444 auto A1 = Builder.buildFMinNumIEEE(Ty, Src0, Src1);
445 auto B1 = Builder.buildFMaxNumIEEE(Ty, Src0, Src1);
418 matchExpandPromotedF16FMed3(MachineInstr &MI, Register Src0, Register Src1, Register Src2) argument
431 applyExpandPromotedF16FMed3(MachineInstr &MI, Register Src0, Register Src1, Register Src2) argument
H A DSIInstrInfo.cpp2670 MachineOperand &Src1,
2737 MachineOperand &Src1 = MI.getOperand(Src1Idx);
2740 if (Src0.isReg() && Src1.isReg()) {
2747 } else if (Src0.isReg() && !Src1.isReg()) {
2750 CommutedMI = swapRegAndNonRegOperand(MI, Src0, Src1);
2751 } else if (!Src0.isReg() && Src1.isReg()) {
2753 CommutedMI = swapRegAndNonRegOperand(MI, Src1, Src0);
2761 Src1, AMDGPU::OpName::src1_modifiers);
3472 MachineOperand *Src1 = getNamedOperand(UseMI, AMDGPU::OpName::src1);
3477 (Src1
[all...]
H A DSIFoldOperands.cpp613 // Special case for s_fmac_f32 if we are trying to fold into Src0 or Src1.
615 // If folding for Src0 happens first and it is identical operand to Src1 we
617 // cause folding into Src1 to fail later on due to wrong OpNo used.
1213 MachineOperand *Src1 = getImmOrMaterializedImm(MI->getOperand(Src1Idx));
1215 if (!Src0->isImm() && !Src1->isImm())
1221 if (Src0->isImm() && Src1->isImm()) {
1223 if (!evalBinaryInstruction(Opc, NewImm, Src0->getImm(), Src1->getImm()))
1239 if (Src0->isImm() && !Src1->isImm()) {
1240 std::swap(Src0, Src1);
1244 int32_t Src1Val = static_cast<int32_t>(Src1
[all...]
H A DSIFixSGPRCopies.cpp711 MachineOperand &Src1 = MI.getOperand(Src1Idx);
716 (Src1.isReg() && TRI->isSGPRReg(*MRI, Src1.getReg()) &&
717 Src1.getReg() != AMDGPU::M0)) {
724 for (MachineOperand *MO : {&Src0, &Src1}) {
749 .add(Src1);
750 Src1.ChangeToRegister(AMDGPU::M0, false);
H A DAMDGPUPostLegalizerCombiner.cpp441 Register Src1 = MI.getOperand(2).getReg(); local
445 if (KB->getKnownBits(Src1).countMinLeadingZeros() >= 32 &&
451 if (KB->computeNumSignBits(Src1) >= 33 &&
/freebsd-current/contrib/llvm-project/llvm/lib/ExecutionEngine/Interpreter/
H A DExecution.cpp105 Dest.TY##Val = Src1.TY##Val OP Src2.TY##Val; \
108 static void executeFAddInst(GenericValue &Dest, GenericValue Src1, argument
119 static void executeFSubInst(GenericValue &Dest, GenericValue Src1, argument
130 static void executeFMulInst(GenericValue &Dest, GenericValue Src1, argument
141 static void executeFDivInst(GenericValue &Dest, GenericValue Src1, argument
152 static void executeFRemInst(GenericValue &Dest, GenericValue Src1, argument
156 Dest.FloatVal = fmod(Src1.FloatVal, Src2.FloatVal);
159 Dest.DoubleVal = fmod(Src1.DoubleVal, Src2.DoubleVal);
169 Dest.IntVal = APInt(1,Src1.IntVal.OP(Src2.IntVal)); \
175 assert(Src1
192 executeICMP_EQ(GenericValue Src1, GenericValue Src2, Type *Ty) argument
206 executeICMP_NE(GenericValue Src1, GenericValue Src2, Type *Ty) argument
220 executeICMP_ULT(GenericValue Src1, GenericValue Src2, Type *Ty) argument
[all...]
/freebsd-current/contrib/llvm-project/llvm/include/llvm/CodeGen/GlobalISel/
H A DMachineIRBuilder.h1094 /// Build and insert \p Res = G_SHUFFLE_VECTOR \p Src1, \p Src2, \p Mask
1099 MachineInstrBuilder buildShuffleVector(const DstOp &Res, const SrcOp &Src1,
1564 const SrcOp &Src1,
1566 return buildInstr(TargetOpcode::G_ADD, {Dst}, {Src0, Src1}, Flags);
1581 const SrcOp &Src1,
1583 return buildInstr(TargetOpcode::G_SUB, {Dst}, {Src0, Src1}, Flags);
1597 const SrcOp &Src1,
1599 return buildInstr(TargetOpcode::G_MUL, {Dst}, {Src0, Src1}, Flags);
1603 const SrcOp &Src1,
1605 return buildInstr(TargetOpcode::G_UMULH, {Dst}, {Src0, Src1}, Flag
1563 buildAdd(const DstOp &Dst, const SrcOp &Src0, const SrcOp &Src1, std::optional<unsigned> Flags = std::nullopt) argument
1580 buildSub(const DstOp &Dst, const SrcOp &Src0, const SrcOp &Src1, std::optional<unsigned> Flags = std::nullopt) argument
1596 buildMul(const DstOp &Dst, const SrcOp &Src0, const SrcOp &Src1, std::optional<unsigned> Flags = std::nullopt) argument
1602 buildUMulH(const DstOp &Dst, const SrcOp &Src0, const SrcOp &Src1, std::optional<unsigned> Flags = std::nullopt) argument
1608 buildSMulH(const DstOp &Dst, const SrcOp &Src0, const SrcOp &Src1, std::optional<unsigned> Flags = std::nullopt) argument
1615 buildURem(const DstOp &Dst, const SrcOp &Src0, const SrcOp &Src1, std::optional<unsigned> Flags = std::nullopt) argument
1621 buildFMul(const DstOp &Dst, const SrcOp &Src0, const SrcOp &Src1, std::optional<unsigned> Flags = std::nullopt) argument
1628 buildFMinNum(const DstOp &Dst, const SrcOp &Src0, const SrcOp &Src1, std::optional<unsigned> Flags = std::nullopt) argument
1634 buildFMaxNum(const DstOp &Dst, const SrcOp &Src0, const SrcOp &Src1, std::optional<unsigned> Flags = std::nullopt) argument
1640 buildFMinNumIEEE(const DstOp &Dst, const SrcOp &Src0, const SrcOp &Src1, std::optional<unsigned> Flags = std::nullopt) argument
1646 buildFMaxNumIEEE(const DstOp &Dst, const SrcOp &Src0, const SrcOp &Src1, std::optional<unsigned> Flags = std::nullopt) argument
1651 buildShl(const DstOp &Dst, const SrcOp &Src0, const SrcOp &Src1, std::optional<unsigned> Flags = std::nullopt) argument
1657 buildLShr(const DstOp &Dst, const SrcOp &Src0, const SrcOp &Src1, std::optional<unsigned> Flags = std::nullopt) argument
1663 buildAShr(const DstOp &Dst, const SrcOp &Src0, const SrcOp &Src1, std::optional<unsigned> Flags = std::nullopt) argument
1680 buildAnd(const DstOp &Dst, const SrcOp &Src0, const SrcOp &Src1) argument
1695 buildOr(const DstOp &Dst, const SrcOp &Src0, const SrcOp &Src1, std::optional<unsigned> Flags = std::nullopt) argument
1702 buildXor(const DstOp &Dst, const SrcOp &Src0, const SrcOp &Src1) argument
1754 buildFAdd(const DstOp &Dst, const SrcOp &Src0, const SrcOp &Src1, std::optional<unsigned> Flags = std::nullopt) argument
1762 buildStrictFAdd(const DstOp &Dst, const SrcOp &Src0, const SrcOp &Src1, std::optional<unsigned> Flags = std::nullopt) argument
1768 buildFSub(const DstOp &Dst, const SrcOp &Src0, const SrcOp &Src1, std::optional<unsigned> Flags = std::nullopt) argument
1775 buildFDiv(const DstOp &Dst, const SrcOp &Src0, const SrcOp &Src1, std::optional<unsigned> Flags = std::nullopt) argument
1782 buildFMA(const DstOp &Dst, const SrcOp &Src0, const SrcOp &Src1, const SrcOp &Src2, std::optional<unsigned> Flags = std::nullopt) argument
1789 buildFMAD(const DstOp &Dst, const SrcOp &Src0, const SrcOp &Src1, const SrcOp &Src2, std::optional<unsigned> Flags = std::nullopt) argument
1847 buildFPow(const DstOp &Dst, const SrcOp &Src0, const SrcOp &Src1, std::optional<unsigned> Flags = std::nullopt) argument
1855 buildFLdexp(const DstOp &Dst, const SrcOp &Src0, const SrcOp &Src1, std::optional<unsigned> Flags = std::nullopt) argument
1868 buildFCopysign(const DstOp &Dst, const SrcOp &Src0, const SrcOp &Src1) argument
1902 buildSMin(const DstOp &Dst, const SrcOp &Src0, const SrcOp &Src1) argument
1908 buildSMax(const DstOp &Dst, const SrcOp &Src0, const SrcOp &Src1) argument
1914 buildUMin(const DstOp &Dst, const SrcOp &Src0, const SrcOp &Src1) argument
1920 buildUMax(const DstOp &Dst, const SrcOp &Src0, const SrcOp &Src1) argument
[all...]
H A DGISelKnownBits.h38 void computeKnownBitsMin(Register Src0, Register Src1, KnownBits &Known,
42 unsigned computeNumSignBitsMin(Register Src0, Register Src1,
H A DMIPatternMatch.h729 Src1Ty Src1; member in struct:llvm::MIPatternMatch::TernaryOp_match
732 TernaryOp_match(const Src0Ty &Src0, const Src1Ty &Src1, const Src2Ty &Src2) argument
733 : Src0(Src0), Src1(Src1), Src2(Src2) {}
740 Src1.match(MRI, TmpMI->getOperand(2).getReg()) &&
750 m_GInsertVecElt(const Src0Ty &Src0, const Src1Ty &Src1, const Src2Ty &Src2) { argument
752 TargetOpcode::G_INSERT_VECTOR_ELT>(Src0, Src1, Src2);
757 m_GISelect(const Src0Ty &Src0, const Src1Ty &Src1, const Src2Ty &Src2) { argument
759 Src0, Src1, Src2);
/freebsd-current/contrib/llvm-project/llvm/lib/Target/AArch64/
H A DAArch64AdvSIMDScalarPass.cpp299 unsigned Src1 = 0, SubReg1; local
328 Src1 = MOSrc1->getReg();
347 if (!Src1) {
349 Src1 = MRI->createVirtualRegister(&AArch64::FPR64RegClass);
350 insertCopy(TII, MI, Src1, OrigSrc1, KillSrc1);
364 .addReg(Src1, getKillRegState(KillSrc1), SubReg1);
/freebsd-current/contrib/llvm-project/llvm/lib/Target/SystemZ/
H A DSystemZSelectionDAGInfo.h39 SDValue Src1, SDValue Src2, SDValue Size,
55 SDValue Src1, SDValue Src2,
H A DSystemZSelectionDAGInfo.cpp173 SelectionDAG &DAG, const SDLoc &DL, SDValue Chain, SDValue Src1,
181 CCReg = emitMemMemImm(DAG, DL, SystemZISD::CLC, Chain, Src2, Src1, Bytes);
183 CCReg = emitMemMemReg(DAG, DL, SystemZISD::CLC, Chain, Src2, Src1, Size);
225 SelectionDAG &DAG, const SDLoc &DL, SDValue Chain, SDValue Src1,
228 SDVTList VTs = DAG.getVTList(Src1.getValueType(), MVT::i32, MVT::Other);
230 SDValue Unused = DAG.getNode(SystemZISD::STRCMP, DL, VTs, Chain, Src2, Src1,
172 EmitTargetCodeForMemcmp( SelectionDAG &DAG, const SDLoc &DL, SDValue Chain, SDValue Src1, SDValue Src2, SDValue Size, MachinePointerInfo Op1PtrInfo, MachinePointerInfo Op2PtrInfo) const argument
224 EmitTargetCodeForStrcmp( SelectionDAG &DAG, const SDLoc &DL, SDValue Chain, SDValue Src1, SDValue Src2, MachinePointerInfo Op1PtrInfo, MachinePointerInfo Op2PtrInfo) const argument
/freebsd-current/contrib/llvm-project/llvm/lib/Target/Hexagon/
H A DHexagonGenMux.cpp134 unsigned getMuxOpcode(const MachineOperand &Src1,
205 unsigned HexagonGenMux::getMuxOpcode(const MachineOperand &Src1, argument
207 bool IsReg1 = Src1.isReg(), IsReg2 = Src2.isReg();
299 MachineOperand *Src1 = &Def1.getOperand(2), *Src2 = &Def2.getOperand(2); local
300 Register SR1 = Src1->isReg() ? Src1->getReg() : Register();
317 MachineOperand *SrcT = (MinX == CI.TrueX) ? Src1 : Src2;
318 MachineOperand *SrcF = (MinX == CI.FalseX) ? Src1 : Src2;
H A DHexagonPeephole.cpp151 MachineOperand &Src1 = MI.getOperand(1); local
153 if (Src1.getImm() != 0)
168 MachineOperand &Src1 = MI.getOperand(1); local
173 Register SrcReg = Src1.getReg();
/freebsd-current/contrib/llvm-project/llvm/lib/Target/PowerPC/
H A DPPCExpandAtomicPseudoInsts.cpp54 Register Src1) {
57 if (Dest0 == Src1 && Dest1 == Src0) {
62 } else if (Dest0 != Src0 || Dest1 != Src1) {
63 if (Dest0 == Src1 || Dest1 != Src0) {
64 BuildMI(MBB, MBBI, DL, OR, Dest1).addReg(Src1).addReg(Src1);
68 BuildMI(MBB, MBBI, DL, OR, Dest1).addReg(Src1).addReg(Src1);
51 PairedCopy(const PPCInstrInfo *TII, MachineBasicBlock &MBB, MachineBasicBlock::iterator MBBI, const DebugLoc &DL, Register Dest0, Register Dest1, Register Src0, Register Src1) argument
/freebsd-current/sys/contrib/edk2/Include/Protocol/
H A DDevicePathUtilities.h54 If Src1 is NULL and Src2 is non-NULL, then a duplicate of Src2 is returned.
55 If Src1 is non-NULL and Src2 is NULL, then a duplicate of Src1 is returned.
56 If Src1 and Src2 are both NULL, then a copy of an end-of-device-path is returned.
58 @param Src1 Points to the first device path.
68 IN CONST EFI_DEVICE_PATH_PROTOCOL *Src1,
/freebsd-current/contrib/llvm-project/llvm/lib/CodeGen/GlobalISel/
H A DCSEMIRBuilder.cpp243 const SrcOp &Src1 = SrcOps[1];
245 ConstantFoldExtOp(Opc, Src0.getReg(), Src1.getImm(), *getMRI()))

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