| /freebsd-current/contrib/llvm-project/clang/lib/StaticAnalyzer/Core/ |
| H A D | RangedConstraintManager.cpp | 49 if (const auto *SSE = dyn_cast<SymSymExpr>(Sym)) {
50 BinaryOperator::Opcode Op = SSE->getOpcode();
54 if (Loc::isLocType(SSE->getLHS()->getType()) &&
55 Loc::isLocType(SSE->getRHS()->getType())) {
66 SymMgr.getSymSymExpr(SSE->getRHS(), BO_Sub, SSE->getLHS(), DiffTy);
78 QualType ExprType = SSE->getType();
80 SymMgr.getSymSymExpr(SSE->getLHS(), BO_EQ, SSE->getRHS(), ExprType);
82 bool WasEqual = SSE
[all...] |
| H A D | RangeConstraintManager.cpp | 1242 RangeSet VisitSymSymExpr(const SymSymExpr *SSE) {
1251 getRangeForNegatedSymSym(SSE),
1255 getRangeForComparisonSymbol(SSE),
1258 getRangeForEqualities(SSE),
1260 VisitBinaryOperator(SSE));
1468 std::optional<RangeSet> getRangeForNegatedSymSym(const SymSymExpr *SSE) {
1470 [SSE, State = this->State]() -> SymbolRef {
1471 if (SSE->getOpcode() == BO_Sub)
1473 SSE->getRHS(), BO_Sub, SSE
[all...] |
| /freebsd-current/contrib/llvm-project/llvm/lib/IR/ |
| H A D | LLVMContextImpl.cpp | 238 for (const auto &SSE : SSC)
239 SSNs[SSE.second] = SSE.first();
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| H A D | VFABIDemangler.cpp | 45 .Case("b", VFISAKind::SSE)
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| /freebsd-current/sys/contrib/openzfs/lib/libspl/include/sys/ |
| H A D | simd.h | 81 SSE = 0, enumerator in enum:cpuid_inst_sets
135 [SSE] = {1U, 0U, 1U << 25, EDX },
209 CPUID_FEATURE_CHECK(sse, SSE);
258 * Check if SSE instruction set is available
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| /freebsd-current/contrib/llvm-project/llvm/include/llvm/IR/ |
| H A D | VFABIDemangler.h | 47 SSE, // x86 SSE member in class:llvm::VFISAKind
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| /freebsd-current/contrib/llvm-project/lldb/source/Plugins/Process/Utility/ |
| H A D | RegisterContext_x86.h | 97 // SSE Registers
160 // SSE Vector Registers
328 SSE = FP << 1, member in class:lldb_private::XSAVE_HDR::XFeature
329 YMM = SSE << 1,
357 // are in FXSAVE.xmm for compatibility with SSE)
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| /freebsd-current/contrib/llvm-project/clang/include/clang/StaticAnalyzer/Core/PathSensitive/ |
| H A D | SMTConstraintManager.h | 285 if (const SymSymExpr *SSE = dyn_cast<SymSymExpr>(BSE))
286 return canReasonAbout(SVB.makeSymbolVal(SSE->getLHS())) &&
287 canReasonAbout(SVB.makeSymbolVal(SSE->getRHS()));
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| /freebsd-current/contrib/llvm-project/clang/lib/CodeGen/Targets/ |
| H A D | X86.cpp | 52 /// Returns true if this type can be passed in SSE registers with the
74 /// Returns true if this aggregate is small enough to be passed in SSE registers
598 // Otherwise, if the type contains an SSE vector type, the alignment is 16.
924 // Since MSVC 2015, the first three SSE vectors have been passed in
1202 SSE, enumerator in enum:__anon561::X86_64ABIInfo::Class
1225 /// final MEMORY or SSE classes when necessary.
1312 /// GCC classifies <1 x long long> as SSE but some platform ABIs choose to
1715 // eightbyte isn't SSE or any other eightbyte isn't SSEUP, the whole
1719 // (d) If SSEUP is not preceded by SSE or SSEUP, it is converted to SSE
[all...] |
| /freebsd-current/sys/contrib/xen/arch-x86/ |
| H A D | cpufeatureset.h | 117 XEN_CPUFEATURE(SSE, 0*32+25) /*A Streaming SIMD Extensions */
173 XEN_CPUFEATURE(SSE4A, 3*32+ 6) /*A SSE-4A */
174 XEN_CPUFEATURE(MISALIGNSSE, 3*32+ 7) /*A Misaligned SSE mode */
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| /freebsd-current/sys/conf/ |
| H A D | kern.mk | 116 # cache tag lines). Explicitly prohibit the use of FPU, SSE and other SIMD
175 # For AMD64, we explicitly prohibit the use of FPU, SSE and other SIMD
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| /freebsd-current/sys/dev/aic7xxx/ |
| H A D | aic7xxx_pci.c | 664 #define SSE 0x40 macro
2027 if (status1 & SSE) {
2048 if ((status1 & (DPE|SSE|RMA|RTA|STA|DPR)) == 0) {
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| H A D | aic79xx_pci.c | 772 #define SSE 0x40 macro
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| H A D | aic79xx_reg.h | 3319 #define SSE 0x40 macro
|