/freebsd-current/contrib/llvm-project/llvm/include/llvm/CodeGen/ |
H A D | VirtRegMap.h | 152 /// records virtReg is a split live interval from SReg. 153 void setIsSplitFromReg(Register virtReg, Register SReg) { argument 154 Virt2SplitMap[virtReg.id()] = SReg; 155 if (hasShape(SReg)) { 156 Virt2ShapeMap[virtReg.id()] = getShape(SReg);
|
/freebsd-current/contrib/llvm-project/llvm/lib/Target/ARM/ |
H A D | A15SDOptimizer.cpp | 100 unsigned getDPRLaneFromSPR(unsigned SReg); 115 unsigned getPrefSPRLane(unsigned SReg); 144 unsigned A15SDOptimizer::getDPRLaneFromSPR(unsigned SReg) { argument 145 unsigned DReg = TRI->getMatchingSuperReg(SReg, ARM::ssub_1, 153 unsigned A15SDOptimizer::getPrefSPRLane(unsigned SReg) { argument 154 if (!Register::isVirtualRegister(SReg)) 155 return getDPRLaneFromSPR(SReg); 157 MachineInstr *MI = MRI->getVRegDef(SReg); 159 MachineOperand *MO = MI->findRegisterDefOperand(SReg); 165 SReg [all...] |
H A D | ARMBaseInstrInfo.cpp | 5075 unsigned SReg, unsigned &Lane) { 5076 unsigned DReg = TRI->getMatchingSuperReg(SReg, ARM::ssub_0, &ARM::DPRRegClass); 5083 DReg = TRI->getMatchingSuperReg(SReg, ARM::ssub_1, &ARM::DPRRegClass); 5074 getCorrespondingDRegAndLane(const TargetRegisterInfo *TRI, unsigned SReg, unsigned &Lane) argument
|
/freebsd-current/contrib/llvm-project/llvm/lib/CodeGen/ |
H A D | RegisterScavenging.cpp | 382 Register SReg = RS.scavengeRegisterBackwards(RC, DefMI.getIterator(), local 384 MRI.replaceRegWith(VReg, SReg); 386 return SReg; 422 Register SReg = scavengeVReg(MRI, RS, Reg, true); local 423 N->addRegisterKilled(SReg, &TRI, false); 424 RS.setRegUsed(SReg); 448 Register SReg = scavengeVReg(MRI, RS, Reg, false); local 449 I->addRegisterDead(SReg, &TRI, false);
|
H A D | LivePhysRegs.cpp | 268 if (any_of(TRI.superregs(Reg), [&](MCPhysReg SReg) { 269 return LiveRegs.contains(SReg) && !MRI.isReserved(SReg);
|
H A D | BranchFolding.cpp | 860 if (any_of(TRI->superregs(Reg), [&](MCPhysReg SReg) { 861 return NewLiveIns.contains(SReg) && !MRI->isReserved(SReg);
|
H A D | PrologEpilogInserter.cpp | 1310 for (MCPhysReg SReg : TRI.sub_and_superregs_inclusive(Reg)) 1311 RegsToZero.reset(SReg);
|
/freebsd-current/contrib/llvm-project/llvm/lib/Target/AMDGPU/ |
H A D | SIPreEmitPeephole.cpp | 128 Register SReg; local 130 SReg = Op2.getReg(); 135 if (M->definesRegister(SReg, TRI)) 137 if (M->modifiesRegister(SReg, TRI)) 139 ReadsSreg |= M->readsRegister(SReg, TRI); 144 // If SReg is VCC and SReg definition is a VALU comparison. 148 if (A->getOpcode() == And && SReg == CondReg && !ModifiesExec && 190 if (SReg == ExecReg) {
|
H A D | SIShrinkInstructions.cpp | 957 Register SReg = Src2->getReg(); local 958 if (SReg.isVirtual()) { 959 MRI->setRegAllocationHint(SReg, 0, VCCReg); 962 if (SReg != VCCReg)
|
H A D | SIInstrInfo.cpp | 1240 Register SReg = MRI.createVirtualRegister(BoolXExecRC); 1241 BuildMI(MBB, I, DL, get(AMDGPU::COPY), SReg) 1248 .addReg(SReg); 1253 Register SReg = MRI.createVirtualRegister(BoolXExecRC); 1255 : AMDGPU::S_CSELECT_B64), SReg) 1263 .addReg(SReg); 1267 Register SReg = MRI.createVirtualRegister(BoolXExecRC); 1269 : AMDGPU::S_CSELECT_B64), SReg) 1277 .addReg(SReg); 1283 Register SReg [all...] |
H A D | SIISelLowering.cpp | 15350 Register SReg = ST.isWave32() 15354 Info->setSGPRForEXECCopy(SReg);
|
/freebsd-current/contrib/llvm-project/clang/include/clang/StaticAnalyzer/Core/PathSensitive/ |
H A D | MemRegion.h | 1035 ParamVarRegion(const Expr *OE, unsigned Idx, const MemRegion *SReg) argument 1036 : VarRegion(SReg, ParamVarRegionKind), OriginExpr(OE), Index(Idx) { 1037 assert(!cast<StackSpaceRegion>(SReg)->getStackFrame()->inTopFrame()); 1042 unsigned Idx, const MemRegion *SReg); 1312 const SubRegion *SReg) 1313 : TypedValueRegion(SReg, CXXBaseObjectRegionKind), Data(RD, IsVirtual) { 1318 bool IsVirtual, const MemRegion *SReg); 1350 CXXDerivedObjectRegion(const CXXRecordDecl *DerivedD, const SubRegion *SReg) argument 1351 : TypedValueRegion(SReg, CXXDerivedObjectRegionKind), DerivedD(DerivedD) { 1356 assert(SReg 1311 CXXBaseObjectRegion(const CXXRecordDecl *RD, bool IsVirtual, const SubRegion *SReg) argument [all...] |
/freebsd-current/contrib/llvm-project/llvm/lib/Target/PowerPC/ |
H A D | PPCRegisterInfo.cpp | 1737 Register SRegHi, SReg, VSReg; local 1744 SRegHi = SReg = is64Bit ? PPC::X4 : PPC::R4; 1745 if (MI.getOperand(0).getReg() == SReg) 1746 SRegHi = SReg = SReg + 1; 1749 .addReg(SReg); 1752 SReg = MF.getRegInfo().createVirtualRegister(RC); 1757 BuildMI(MBB, II, dl, TII.get(is64Bit ? PPC::LI8 : PPC::LI), SReg) 1762 BuildMI(MBB, II, dl, TII.get(is64Bit ? PPC::ORI8 : PPC::ORI), SReg) 1767 TII.materializeImmPostRA(MBB, II, dl, SReg, Offse [all...] |
H A D | PPCISelLowering.cpp | 12174 Register SReg = RegInfo.createVirtualRegister(GPRC); local 12176 BuildMI(BB, dl, TII->get(PPC::AND), SReg) 12179 unsigned ValueReg = SReg; 12184 .addReg(SReg)
|
/freebsd-current/contrib/llvm-project/clang/lib/StaticAnalyzer/Core/ |
H A D | MemRegion.cpp | 320 unsigned Idx, const MemRegion *SReg) { 324 ID.AddPointer(SReg); 422 const MemRegion *SReg) { 425 ID.AddPointer(SReg); 434 const MemRegion *SReg) { 436 ID.AddPointer(SReg); 319 ProfileRegion(llvm::FoldingSetNodeID &ID, const Expr *OE, unsigned Idx, const MemRegion *SReg) argument 419 ProfileRegion(llvm::FoldingSetNodeID &ID, const CXXRecordDecl *RD, bool IsVirtual, const MemRegion *SReg) argument 432 ProfileRegion(llvm::FoldingSetNodeID &ID, const CXXRecordDecl *RD, const MemRegion *SReg) argument
|
/freebsd-current/contrib/llvm-project/llvm/lib/Target/Mips/AsmParser/ |
H A D | MipsAsmParser.cpp | 4931 unsigned SReg = Inst.getOperand(1).getReg(); local 4939 if (DReg == SReg) { 4947 TOut.emitRRR(Mips::ROTRV, DReg, SReg, TmpReg, Inst.getLoc(), STI); 4952 TOut.emitRRR(Mips::ROTRV, DReg, SReg, TReg, Inst.getLoc(), STI); 4978 TOut.emitRRR(FirstShift, ATReg, SReg, ATReg, Inst.getLoc(), STI); 4979 TOut.emitRRR(SecondShift, DReg, SReg, TReg, Inst.getLoc(), STI); 4994 unsigned SReg = Inst.getOperand(1).getReg(); local 5006 TOut.emitRRI(Mips::ROTR, DReg, SReg, ShiftValue, Inst.getLoc(), STI); 5011 TOut.emitRRI(Mips::ROTR, DReg, SReg, ImmValue, Inst.getLoc(), STI); 5020 TOut.emitRRI(Mips::SRL, DReg, SReg, 5056 unsigned SReg = Inst.getOperand(1).getReg(); local 5119 unsigned SReg = Inst.getOperand(1).getReg(); local [all...] |