Searched refs:RW (Results 1 - 25 of 42) sorted by relevance

12

/freebsd-current/sys/contrib/ck/include/
H A Dck_rwcohort.h44 #define CK_RWCOHORT_WP_INIT(N, RW, WL) ck_rwcohort_wp_##N##_init(RW, WL)
45 #define CK_RWCOHORT_WP_READ_LOCK(N, RW, C, GC, LC) \
46 ck_rwcohort_wp_##N##_read_lock(RW, C, GC, LC)
47 #define CK_RWCOHORT_WP_READ_UNLOCK(N, RW, C, GC, LC) \
48 ck_rwcohort_wp_##N##_read_unlock(RW)
49 #define CK_RWCOHORT_WP_WRITE_LOCK(N, RW, C, GC, LC) \
50 ck_rwcohort_wp_##N##_write_lock(RW, C, GC, LC)
51 #define CK_RWCOHORT_WP_WRITE_UNLOCK(N, RW, C, GC, LC) \
52 ck_rwcohort_wp_##N##_write_unlock(RW,
[all...]
/freebsd-current/sys/contrib/openzfs/tests/zfs-tests/tests/functional/cli_root/zpool_events/
H A Dzpool_events_duplicates.ksh79 RW=$2
81 log_note "Testing $ERR $RW ereports"
86 if [ "$RW" == "read" ] ; then
109 log_must zinject -d $VDEV1 -e $ERR -T $RW -f 100 $POOL
111 if [ "$RW" == "write" ] ; then
121 log_note "$actual total $ERR $RW ereports where $unique were unique"
124 log_note "UNEXPECTED -- $((actual-unique)) duplicate $ERR $RW ereports"
H A Dzpool_events_errors.ksh85 RW=$3
87 log_note "Testing $ERR $RW on $POOLTYPE"
92 if [ "$RW" == "read" ] ; then
96 log_must zinject -d $VDEV1 -e $ERR -T $RW -f 100 $POOL
98 if [ "$RW" == "write" ] ; then
124 if [ "$RW" == "read" ] ; then
/freebsd-current/sys/contrib/openzfs/tests/zfs-tests/tests/functional/cli_root/zfs_mount/
H A Dzfs_mount_remount.ksh58 typeset RW="-t zfs -uw"
61 typeset RW="-o remount,rw"
124 log_must mount $RW $TESTFS $MNTPFS
145 log_mustnot mount $RW $TESTSNAP $MNTPSNAP
167 log_mustnot mount $RW $MNTPFS
/freebsd-current/sys/dev/rtwn/rtl8192c/
H A Dr92c_chan.c164 reg = RW(reg, R92C_TXAGC_A_CCK1, power[RTWN_RIDX_CCK1]);
167 reg = RW(reg, R92C_TXAGC_A_CCK2, power[RTWN_RIDX_CCK2]);
168 reg = RW(reg, R92C_TXAGC_A_CCK55, power[RTWN_RIDX_CCK55]);
169 reg = RW(reg, R92C_TXAGC_A_CCK11, power[RTWN_RIDX_CCK11]);
173 reg = RW(reg, R92C_TXAGC_B_CCK1, power[RTWN_RIDX_CCK1]);
174 reg = RW(reg, R92C_TXAGC_B_CCK2, power[RTWN_RIDX_CCK2]);
175 reg = RW(reg, R92C_TXAGC_B_CCK55, power[RTWN_RIDX_CCK55]);
178 reg = RW(reg, R92C_TXAGC_B_CCK11, power[RTWN_RIDX_CCK11]);
304 RW(rs->rf_chnlbw[i], R92C_RF_CHNLBW_CHNL, chan));
H A Dr92c_rf.c68 RW(reg[chain], R92C_HSSI_PARAM2_READ_ADDR, addr) |
/freebsd-current/usr.bin/bintrans/
H A Duuencode.c127 #define RW (S_IRUSR|S_IWUSR|S_IRGRP|S_IWGRP|S_IROTH|S_IWOTH) macro
128 mode = RW & ~umask(RW);
/freebsd-current/contrib/ntp/ntpd/
H A Dcmd_args.c160 set_sys_var(v_assign, strlen(v_assign) + 1, RW);
172 (u_short) (RW | DEF));
/freebsd-current/contrib/llvm-project/llvm/lib/MC/MCDisassembler/
H A DMCDisassembler.cpp65 SMC_PCASE(RW, 1)
/freebsd-current/sys/dev/rtwn/rtl8188e/
H A Dr88e_init.c66 RW(reg, R92C_AFE_XTAL_CTRL_ADDR, val | val << 6));
/freebsd-current/sys/dev/rtwn/rtl8192e/
H A Dr92e_rf.c64 RW(val, R92C_HSSI_PARAM2_READ_ADDR, addr) &
H A Dr92e_chan.c220 RW(rs->rf_chnlbw[0], R92C_RF_CHNLBW_CHNL, chan));
/freebsd-current/contrib/llvm-project/llvm/lib/Target/Hexagon/
H A DHexagonBitTracker.cpp94 uint16_t RW = getRegBitWidth(RegisterRef(Reg, Sub)); local
101 return IsSubLo ? BT::BitMask(0, RW-1)
102 : BT::BitMask(RW, 2*RW-1);
274 // Extract RW low bits of the cell.
275 auto lo = [this] (const BT::RegisterCell &RC, uint16_t RW)
277 assert(RW <= RC.width());
278 return eXTR(RC, 0, RW);
280 // Extract RW high bits of the cell.
281 auto hi = [this] (const BT::RegisterCell &RC, uint16_t RW)
[all...]
H A DHexagonBitSimplify.cpp1587 unsigned RW = RC.width();
1588 if (W == RW) {
1602 if (W*2 != RW)
2431 unsigned RW = W;
2491 if (Len == RW)
2514 if (SW < RW || (SW % RW) != 0)
2522 unsigned OE = (Off+Len)/RW;
2523 if (OE != Off/RW) {
2526 // size RW, an
[all...]
/freebsd-current/contrib/llvm-project/openmp/runtime/src/
H A Dz_AIX_asm.S399 .csect __kmp_unnamed_critical_addr[RW],3
401 .csect __kmp_unnamed_critical_addr[RW],2
403 .globl __kmp_unnamed_critical_addr[RW]
/freebsd-current/sys/dev/aic7xxx/aicasm/
H A Daicasm_symbol.h67 RW = 0x03 enumerator in enum:__anon1659
H A Daicasm_scan.l171 RW|RO|WO {
172 if (strcmp(yytext, "RW") == 0)
173 yylval.value = RW;
/freebsd-current/sys/dev/rtwn/
H A Dif_rtwnreg.h113 #define RW(var, field, val) \ macro
H A Dif_rtwn_efuse.c91 reg = RW(reg, R92C_EFUSE_CTRL_ADDR, sc->next_rom_addr);
H A Dif_rtwn_fw.c64 reg = RW(reg, R92C_MCUFWDL_PAGE, page);
/freebsd-current/contrib/llvm-project/lldb/source/Plugins/Instruction/ARM64/
H A DEmulateInstructionARM64.h147 RW : 1, // Current register width ��� 0 is AArch64, 1 is AArch32 member in struct:EmulateInstructionARM64::__anon1270
/freebsd-current/contrib/llvm-project/llvm/lib/CodeGen/
H A DMLRegAllocEvictAdvisor.cpp272 double RW = 0; member in struct:__anon1892::LIFeatureComponents
824 Ret.RW += (Reads && Writes) * Freq;
852 double RW = 0.0; local
888 RW += LIFC.RW;
930 SET(weighed_read_writes_by_max, float, RW);
/freebsd-current/contrib/llvm-project/llvm/utils/TableGen/
H A DCodeGenSchedule.cpp604 // Visit each RW in the sequence selected by the current variant.
628 for (Record *RW : RWs) {
629 if (RW->isSubClassOf("SchedWrite"))
630 scanSchedRW(RW, SWDefs, RWSet);
632 assert(RW->isSubClassOf("SchedRead") && "Unknown SchedReadWrite");
633 scanSchedRW(RW, SRDefs, RWSet);
708 CodeGenSchedRW &RW = getSchedRW(MatchDef); local
709 if (RW.IsAlias)
711 RW.Aliases.push_back(ADef);
751 RWVec, [Def](const CodeGenSchedRW &RW) { retur
[all...]
/freebsd-current/contrib/llvm-project/llvm/lib/BinaryFormat/
H A DXCOFF.cpp32 SMC_CASE(RW)
/freebsd-current/sys/dev/rtwn/rtl8821a/
H A Dr21a_init.c327 reg = RW(reg, R21A_MAC_PHY_CRYSTALCAP, val | (val << 6));

Completed in 334 milliseconds

12