Searched refs:RISCVISD (Results 1 - 3 of 3) sorted by relevance

/freebsd-current/contrib/llvm-project/llvm/lib/Target/RISCV/
H A DRISCVISelLowering.cpp821 // Integer VTs are lowered as a series of "RISCVISD::TRUNCATE_VECTOR_VL"
2593 return DAG.getNode(RISCVISD::VMSET_VL, DL, MaskVT, VL);
2755 Opc = IsSigned ? RISCVISD::FCVT_X : RISCVISD::FCVT_XU;
2757 Opc = IsSigned ? RISCVISD::FCVT_W_RV64 : RISCVISD::FCVT_WU_RV64;
2767 if (Opc == RISCVISD::FCVT_WU_RV64)
2806 SDValue IsNan = DAG.getNode(RISCVISD::SETCC_VL, DL, Mask.getValueType(),
2815 Src = DAG.getNode(RISCVISD::FP_EXTEND_VL, DL, InterVT, Src, Mask, VL);
2819 IsSigned ? RISCVISD
[all...]
H A DRISCVISelDAGToDAG.cpp66 VT.isInteger() ? RISCVISD::VMV_V_X_VL : RISCVISD::VFMV_V_F_VL;
76 case RISCVISD::SPLAT_VECTOR_SPLIT_I64_VL: {
952 case RISCVISD::SplitF64: {
2091 case RISCVISD::VMV_S_X_VL:
2092 case RISCVISD::VFMV_S_F_VL:
2093 case RISCVISD::VMV_V_X_VL:
2094 case RISCVISD::VFMV_V_F_VL: {
2096 bool IsScalarMove = Node->getOpcode() == RISCVISD::VMV_S_X_VL ||
2097 Node->getOpcode() == RISCVISD
[all...]
H A DRISCVISelLowering.h29 namespace RISCVISD { namespace in namespace:llvm
429 } // namespace RISCVISD

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