Searched refs:RD4 (Results 1 - 25 of 81) sorted by relevance

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/freebsd-current/sys/arm/freescale/imx/
H A Dimx6_ccm.c66 RD4(struct ccm_softc *sc, bus_size_t off) function
177 reg = RD4(sc, CCM_CGPR);
180 reg = RD4(sc, CCM_CLPCR);
224 reg = RD4(sc, CCM_CSCMR1);
239 reg = RD4(sc, CCM_CS1CDR);
253 reg = RD4(sc, CCM_CS2CDR);
271 WR4(ccm_sc, CCM_CCGR6, RD4(ccm_sc, CCM_CCGR6) | CCGR_CLK_MODE_ALWAYS);
325 WR4(ccm_sc, CCM_CCGR5, RD4(ccm_sc, CCM_CCGR5) | CCGR5_SATA);
328 v = RD4(ccm_sc, CCM_ANALOG_PLL_ENET);
333 if (RD4(ccm_s
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H A Dimx6_snvs.c80 RD4(struct snvs_softc *sc, bus_size_t offset) function
106 while ((RD4(sc, SNVS_LPCR) & LPCR_SRTC_ENV) != enbit)
119 if (!(RD4(sc, SNVS_LPCR) & LPCR_SRTC_ENV)) {
131 counter1 = (uint64_t)RD4(sc, SNVS_LPSRTCMR) << (SBT_LSB + 32);
132 counter1 |= (uint64_t)RD4(sc, SNVS_LPSRTCLR) << (SBT_LSB);
133 counter2 = (uint64_t)RD4(sc, SNVS_LPSRTCMR) << (SBT_LSB + 32);
134 counter2 |= (uint64_t)RD4(sc, SNVS_LPSRTCLR) << (SBT_LSB);
H A Dimx6_src.c57 RD4(struct src_softc *sc, bus_size_t off) function
79 reg = RD4(src_sc, SRC_SCR);
84 reg = RD4(src_sc, SRC_SCR);
/freebsd-current/sys/arm/nvidia/
H A Dtegra_efuse.c50 #define RD4(_sc, _r) bus_read_4((_sc)->mem_res, (FUSES_START + (_r))) macro
194 sku->sku_id = RD4(sc, TEGRA124_FUSE_SKU_INFO);
195 sku->soc_iddq_value = RD4(sc, TEGRA124_FUSE_SOC_IDDQ);
196 sku->cpu_iddq_value = RD4(sc, TEGRA124_FUSE_CPU_IDDQ);
197 sku->gpu_iddq_value = RD4(sc, TEGRA124_FUSE_GPU_IDDQ);
198 sku->soc_speedo_value = RD4(sc, TEGRA124_FUSE_SOC_SPEEDO_0);
199 sku->cpu_speedo_value = RD4(sc, TEGRA124_FUSE_CPU_SPEEDO_0);
200 sku->gpu_speedo_value = RD4(sc, TEGRA124_FUSE_CPU_SPEEDO_2);
284 reg = RD4(sc, TEGRA210_FUSE_SPARE + 2 * 4);
286 reg = RD4(s
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H A Dtegra_usbphy.c306 #define RD4(sc, offs) \ macro
318 if ((RD4(sc, reg) & mask) == val)
331 val = RD4(sc, CTRL_USB_HOSTPC1_DEVLC);
354 val = RD4(sc, IF_USB_SUSP_CTRL);
358 val = RD4(sc, UTMIP_TX_CFG0);
362 val = RD4(sc, UTMIP_HSRX_CFG0);
369 val = RD4(sc, UTMIP_HSRX_CFG1);
374 val = RD4(sc, UTMIP_DEBOUNCE_CFG0);
379 val = RD4(sc, UTMIP_MISC_CFG0);
384 val = RD4(s
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/freebsd-current/sys/arm64/nvidia/tegra210/
H A Dtegra210_xusbpadctl.c325 #define RD4(_sc, _r) bus_read_4((_sc)->mem_res, (_r)) macro
570 reg = RD4(sc, XUSB_PADCTL_UPHY_PLL_P0_CTL2);
575 reg = RD4(sc, XUSB_PADCTL_UPHY_PLL_P0_CTL5);
580 reg = RD4(sc, XUSB_PADCTL_UPHY_PLL_P0_CTL1);
584 reg = RD4(sc, XUSB_PADCTL_UPHY_PLL_P0_CTL2);
588 reg = RD4(sc, XUSB_PADCTL_UPHY_PLL_P0_CTL8);
596 reg = RD4(sc, XUSB_PADCTL_UPHY_PLL_P0_CTL4);
603 reg = RD4(sc, XUSB_PADCTL_UPHY_PLL_P0_CTL1);
609 reg = RD4(sc, XUSB_PADCTL_UPHY_PLL_P0_CTL1);
613 reg = RD4(s
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H A Dtegra210_pmc.c203 RD4(struct tegra210_pmc_softc *sc, bus_size_t r) function
227 reg = RD4(sc, PMC_PWRGATE_STATUS) & PMC_PWRGATE_STATUS_PARTID(id);
234 reg = RD4(sc, PMC_PWRGATE_TOGGLE);
247 reg = RD4(sc, PMC_PWRGATE_TOGGLE);
274 reg = RD4(sc, PMC_PWRGATE_STATUS);
287 reg = RD4(sc, PMC_REMOVE_CLAMPING_CMD);
295 reg = RD4(sc, PMC_CLAMP_STATUS);
310 reg = RD4(sc, PMC_PWRGATE_STATUS);
505 orig = RD4(sc, PMC_SCRATCH0);
507 if (RD4(s
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H A Dtegra210_clk_pll.c603 RD4(sc, sc->base_reg, &reg);
616 RD4(sc, sc->base_reg, &reg);
688 RD4(sc, sc->base_reg, &val);
714 RD4(sc, sc->misc_reg, &reg);
719 RD4(sc, sc->misc_reg, &reg);
724 RD4(sc, sc->base_reg, &reg);
758 RD4(sc, sc->base_reg, &reg);
763 RD4(sc, PLLE_AUX, &reg);
769 RD4(sc, sc->misc_reg, &reg);
779 RD4(s
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/freebsd-current/sys/arm/mv/clk/
H A Da37x0_tbg_pll.c42 #define RD4(_clk, offset, val) \ macro
61 RD4(clk, sc->tbg_bypass.offset, &val);
65 RD4(clk, sc->vcodiv.offset, &val);
68 RD4(clk, sc->refdiv.offset, &val);
71 RD4(clk, sc->fbdiv.offset, &val);
H A Darmada38x_gen.c47 #define RD4(_clk, offset, val) \ macro
60 RD4(clk, 0, &reg);
/freebsd-current/sys/arm/broadcom/bcm2835/
H A Dbcm2835_sdhost.c233 RD4(struct bcm_sdhost_softc *sc, bus_size_t off) function
255 val = RD4(sc, off & ~3);
266 val = RD4(sc, off & ~3);
276 val32 = RD4(sc, off & ~3);
287 val32 = RD4(sc, off & ~3);
302 RD4(sc, HC_COMMAND));
304 RD4(sc, HC_ARGUMENT));
306 RD4(sc, HC_TIMEOUTCOUNTER));
308 RD4(sc, HC_CLOCKDIVISOR));
310 RD4(s
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/freebsd-current/sys/arm/nvidia/tegra124/
H A Dtegra124_clk_pll.c417 RD4(sc, sc->base_reg, &reg);
430 RD4(sc, sc->base_reg, &reg);
495 RD4(sc, sc->base_reg, &val);
521 RD4(sc, sc->misc_reg, &reg);
526 RD4(sc, sc->misc_reg, &reg);
531 RD4(sc, sc->base_reg, &reg);
566 RD4(sc, sc->base_reg, &reg);
570 RD4(sc, PLLE_AUX, &reg);
576 RD4(sc, sc->misc_reg, &reg);
586 RD4(s
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H A Dtegra124_pmc.c136 #define RD4(_sc, _r) bus_read_4((_sc)->mem_res, (_r)) macro
191 reg = RD4(sc, PMC_PWRGATE_STATUS) & PMC_PWRGATE_STATUS_PARTID(id);
198 reg = RD4(sc, PMC_PWRGATE_TOGGLE);
211 reg = RD4(sc, PMC_PWRGATE_TOGGLE);
238 reg = RD4(sc, PMC_PWRGATE_STATUS);
251 reg = RD4(sc, PMC_REMOVE_CLAMPING_CMD);
259 reg = RD4(sc, PMC_CLAMP_STATUS);
274 reg = RD4(sc, PMC_PWRGATE_STATUS);
512 reg = RD4(sc, PMC_CNTRL);
517 reg = RD4(s
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H A Dtegra124_xusbpadctl.c171 #define RD4(_sc, _r) bus_read_4((_sc)->mem_res, (_r)) macro
368 reg = RD4(sc, XUSB_PADCTL_SS_PORT_MAP);
377 reg = RD4(sc, XUSB_PADCTL_IOPHY_USB3_PAD_CTL2(port->idx));
389 reg = RD4(sc, XUSB_PADCTL_ELPG_PROGRAM);
394 reg = RD4(sc, XUSB_PADCTL_ELPG_PROGRAM);
399 reg = RD4(sc, XUSB_PADCTL_ELPG_PROGRAM);
413 reg = RD4(sc, XUSB_PADCTL_IOPHY_PLL_P0_CTL1);
418 reg = RD4(sc, XUSB_PADCTL_IOPHY_PLL_P0_CTL2);
425 reg = RD4(sc, XUSB_PADCTL_IOPHY_PLL_P0_CTL1);
431 reg = RD4(s
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/freebsd-current/sys/dev/sdhci/
H A Dsdhci_fsl_fdt.c56 #define RD4 (sc->read) macro
292 if (RD4(sc, SDHCI_FSL_PRES_STATE) & SDHCI_FSL_PRES_SDSTB)
294 if (RD4(sc, SDHCI_FSL_SYS_CTRL) & SDHCI_FSL_CLK_SDCLKEN)
322 val32 = RD4(sc, SDHCI_CLOCK_CONTROL);
385 wrk32 = RD4(sc, SDHCI_FSL_PROT_CTRL);
399 return ((RD4(sc, off & ~3) >> (off & 3) * 8) & UINT8_MAX);
414 return (RD4(sc, SDHCI_FSL_HOST_VERSION) & UINT16_MAX);
424 val32 = RD4(sc, SDHCI_INT_STATUS);
425 val32 &= RD4(sc, SDHCI_SIGNAL_ENABLE);
428 return ((RD4(s
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H A Dfsl_sdhci.c190 RD4(struct fsl_sdhci_softc *sc, bus_size_t off) function
215 wrk32 = RD4(sc, SDHC_PROT_CTRL);
254 return ((RD4(sc, off & ~3) >> (off & 3) * 8) & 0xff);
276 return (RD4(sc, USDHC_MIX_CONTROL) & 0x37);
298 val32 = RD4(sc, SDHCI_INT_STATUS);
299 val32 &= RD4(sc, SDHCI_SIGNAL_ENABLE);
311 return ((RD4(sc, off & ~3) >> (off & 3) * 8) & 0xffff);
320 val32 = RD4(sc, off);
388 val32 = RD4(sc, SDHC_PROT_CTRL);
412 val32 = RD4(s
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/freebsd-current/sys/arm/mv/
H A Dmv_thermal.c121 #define RD4(sc, reg) \ macro
142 reg = RD4(sc, STATUS);
163 reg = RD4(sc, CONTROL0);
185 reg = RD4(sc, CONTROL0);
202 reg = RD4(sc, STATUS) & STATUS_TEMP_MASK;
221 reg = RD4(sc, CONTROL0);
241 reg = RD4(sc, CONTROL1);
247 reg = RD4(sc, CONTROL0);
/freebsd-current/sys/arm/xilinx/
H A Dzy7_slcr.c73 #define RD4(sc, off) (bus_read_4((sc)->mem_res, (off))) macro
137 RD4(sc, ZY7_SLCR_REBOOT_STAT) & 0xf0ffffff);
271 reg = RD4(sc, ZY7_SLCR_FPGA_CLK_CTRL(unit));
297 reg = RD4(sc, ZY7_SLCR_FPGA_CLK_CTRL(unit));
361 reg = RD4(sc, ZY7_SLCR_FPGA_CLK_CTRL(unit));
410 reg = RD4(sc, ZY7_SLCR_FPGA_CLK_CTRL(unit));
490 reg = RD4(sc, ZY7_SLCR_FPGA_THR_CNT(unit));
507 reg = RD4(sc, ZY7_SLCR_LVL_SHFTR_EN);
596 bootmode = RD4(sc, ZY7_SLCR_BOOT_MODE);
601 pss_idcode = RD4(s
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/freebsd-current/sys/dev/cadence/
H A Dif_cgem.c220 #define RD4(sc, off) (bus_read_4((sc)->mem_res, (off))) macro
251 uint32_t low = RD4(sc, CGEM_SPEC_ADDR_LOW(i));
252 uint32_t high = RD4(sc, CGEM_SPEC_ADDR_HI(i)) & 0xffff;
384 queue_mask = (RD4(sc, CGEM_DESIGN_CFG6) &
881 sc->stats.tx_bytes += RD4(sc, CGEM_OCTETS_TX_BOT);
882 sc->stats.tx_bytes += (uint64_t)RD4(sc, CGEM_OCTETS_TX_TOP) << 32;
884 sc->stats.tx_frames += RD4(sc, CGEM_FRAMES_TX);
885 sc->stats.tx_frames_bcast += RD4(sc, CGEM_BCAST_FRAMES_TX);
886 sc->stats.tx_frames_multi += RD4(sc, CGEM_MULTI_FRAMES_TX);
887 sc->stats.tx_frames_pause += RD4(s
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/freebsd-current/sys/dev/clk/
H A Dclk_mux.c41 #define RD4(_clk, off, val) \ macro
80 rv = RD4(clk, sc->offset, &reg);
106 RD4(clk, sc->offset, &reg);
/freebsd-current/sys/dev/clk/rockchip/
H A Drk_clk_gate.c41 #define RD4(_clk, off, val) \ macro
80 rv = RD4(clk, sc->offset, &reg);
107 RD4(clk, sc->offset, &reg);
/freebsd-current/sys/arm64/freescale/imx/clk/
H A Dimx_clk_mux.c45 #define RD4(_clk, off, val) \ macro
83 rv = RD4(clk, sc->offset, &reg);
109 RD4(clk, sc->offset, &reg);
/freebsd-current/sys/dev/eqos/
H A Dif_eqos.c97 #define RD4(sc, o) bus_read_4(sc->res[EQOS_RES_MEM], (o)) macro
126 addr = RD4(sc, GMAC_MAC_MDIO_ADDRESS);
128 val = RD4(sc, GMAC_MAC_MDIO_DATA) & 0xFFFF;
159 addr = RD4(sc, GMAC_MAC_MDIO_ADDRESS);
186 reg = RD4(sc, GMAC_MAC_CONFIGURATION);
418 pfil = RD4(sc, GMAC_MAC_PACKET_FILTER);
461 val = RD4(sc, GMAC_DMA_MODE);
508 val = RD4(sc, GMAC_DMA_CHAN0_CONTROL);
513 val = RD4(sc, GMAC_DMA_CHAN0_TX_CONTROL);
517 val = RD4(s
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/freebsd-current/sys/dev/hwpmc/
H A Dpmu_dmc620.c69 #define RD4(sc, r) bus_read_4((sc)->sc_res[0], (r)) macro
71 #define MD4(sc, r, c, s) WR4((sc), (r), (RD4((sc), (r)) & ~(c)) | (s))
87 val = RD4(sc, DMC620_REG(cntr, reg));
215 clkdiv2_stat = RD4(sc, DMC620_OVERFLOW_STATUS_CLKDIV2);
216 clk_stat = RD4(sc, DMC620_OVERFLOW_STATUS_CLK);
222 sc->sc_saved_control[i] = RD4(sc, DMC620_REG(i,
/freebsd-current/sys/dev/ffec/
H A Dif_ffec.c224 RD4(struct ffec_softc *sc, bus_size_t off) function
310 if (RD4(sc, FEC_IER_REG) & FEC_IER_MII)
336 val = RD4(sc, FEC_MMFR_REG) & FEC_MMFR_DATA_MASK;
387 ecr = RD4(sc, FEC_ECR_REG) & ~FEC_ECR_SPEED;
388 rcr = RD4(sc, FEC_RCR_REG) & ~(FEC_RCR_RMII_10T | FEC_RCR_RMII_MODE |
390 tcr = RD4(sc, FEC_TCR_REG) & ~FEC_TCR_FDEN;
482 mibc = RD4(sc, FEC_MIBC_REG);
529 if_inc_counter(ifp, IFCOUNTER_IPACKETS, RD4(sc, FEC_RMON_R_PACKETS));
530 if_inc_counter(ifp, IFCOUNTER_IMCASTS, RD4(sc, FEC_RMON_R_MC_PKT));
532 RD4(s
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