/freebsd-current/contrib/llvm-project/llvm/lib/Target/Hexagon/ |
H A D | HexagonMachineScheduler.cpp | 28 const auto *QII = static_cast<const HexagonInstrInfo *>(TII); local 31 if (QII->mayBeCurLoad(*SUd->getInstr())) 34 if (QII->canExecuteInBundle(*SUd->getInstr(), *SUu->getInstr())) 56 auto &QII = *QST.getInstrInfo(); local 57 if (SU->isInstr() && QII.mayBeCurLoad(*SU->getInstr())) {
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H A D | HexagonVectorPrint.cpp | 54 const HexagonInstrInfo *QII = nullptr; member in class:__anon2440::HexagonVectorPrint 98 const DebugLoc &DL, const HexagonInstrInfo *QII, 103 BuildMI(*MBB, I, DL, QII->get(TargetOpcode::INLINEASM)) 135 QII = QST->getInstrInfo(); 185 addAsmInstr(MBB, Reg, MII, DL, QII, Fn); 189 MII, DL, QII, Fn); 191 MII, DL, QII, Fn); 194 addAsmInstr(MBB, Reg, MII, DL, QII, Fn); 96 addAsmInstr(MachineBasicBlock *MBB, unsigned Reg, MachineBasicBlock::instr_iterator I, const DebugLoc &DL, const HexagonInstrInfo *QII, MachineFunction &Fn) argument
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H A D | HexagonPeephole.cpp | 82 const HexagonInstrInfo *QII; member in struct:__anon2431::HexagonPeephole 113 QII = static_cast<const HexagonInstrInfo *>(MF.getSubtarget().getInstrInfo()); 231 if (QII->isPredicated(MI)) { 244 int NewOp = QII->getInvertedPredicatedOpcode(MI.getOpcode()); 245 MI.setDesc(QII->get(NewOp)); 273 BuildMI(MBB, MI.getIterator(), MI.getDebugLoc(), QII->get(NewOp),
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H A D | HexagonNewValueJump.cpp | 95 const HexagonInstrInfo *QII; member in struct:__anon2430::HexagonNewValueJump 116 static bool canBeFeederToNewValueJump(const HexagonInstrInfo *QII, argument 123 if (QII->isPredicated(*II)) 142 if (QII->isSolo(*II)) 145 if (QII->isFloat(*II)) 237 static bool canCompareBeNewValueJump(const HexagonInstrInfo *QII, argument 459 QII = static_cast<const HexagonInstrInfo *>(MF.getSubtarget().getInstrInfo()); 570 if (!canCompareBeNewValueJump(QII, QRI, MII, predReg, isSecondOpReg, 611 if (!canBeFeederToNewValueJump(QII, QRI, MII, jmpPos, cmpPos, MF)) { 621 if (!canBeFeederToNewValueJump(QII, QR [all...] |
H A D | HexagonSubtarget.cpp | 269 auto *QII = static_cast<const HexagonInstrInfo*>(DAG->TII); local 272 if (!QII->isHVXVec(MI1) || !(IsStoreMI1 || IsLoadMI1)) 278 if (!QII->isHVXVec(MI2)) 447 const HexagonInstrInfo *QII = getInstrInfo(); local 452 if (QII->canExecuteInBundle(*SrcInst, *DstInst) && 453 isBestZeroLatency(Src, Dst, QII, ExclSrc, ExclDst)) { 505 if (EnableDotCurSched && QII->isToBeScheduledASAP(*SrcInst, *DstInst) && 506 isBestZeroLatency(Src, Dst, QII, ExclSrc, ExclDst)) { 550 auto &QII = static_cast<const HexagonInstrInfo &>(*getInstrInfo()); 552 if (QII [all...] |
H A D | HexagonVLIWPacketizer.cpp | 949 const HexagonInstrInfo *QII) { 952 assert(QII->isPredicated(MI) && "Must be predicated instruction"); 948 getPredicatedRegister(MachineInstr &MI, const HexagonInstrInfo *QII) argument
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