| /freebsd-current/contrib/llvm-project/llvm/lib/Target/Mips/ |
| H A D | MicroMipsSizeReduction.cpp | 197 MachineInstr *MI2 = nullptr,
398 static bool ConsecutiveInstr(MachineInstr *MI1, MachineInstr *MI2) { argument
403 if (!GetImm(MI2, 2, Offset2))
407 Register Reg2 = MI2->getOperand(0).getReg();
465 MachineInstr *MI2 = &*NextMII; local
475 if (!CheckXWPInstr(MI2, ReduceToLwp, Entry))
479 Register Reg2 = MI2->getOperand(1).getReg();
484 bool ConsecutiveForward = ConsecutiveInstr(MI1, MI2);
485 bool ConsecutiveBackward = ConsecutiveInstr(MI2, MI1);
491 return ReplaceInstruction(MI1, Entry, MI2, ConsecutiveForwar
622 MachineInstr *MI2 = &*NextMII; local
693 ReplaceInstruction(MachineInstr *MI, const ReduceEntry &Entry, MachineInstr *MI2, bool ConsecutiveForward) argument
[all...] |
| /freebsd-current/contrib/llvm-project/llvm/lib/CodeGen/ |
| H A D | DFAPacketizer.cpp | 272 const MachineInstr &MI2,
274 if (MI1.memoperands_empty() || MI2.memoperands_empty())
278 for (const MachineMemOperand *Op2 : MI2.memoperands())
271 alias(const MachineInstr &MI1, const MachineInstr &MI2, bool UseTBAA) const argument
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| H A D | TargetInstrInfo.cpp | 842 MachineInstr *MI2 = nullptr; local
846 MI2 = MRI.getUniqueVRegDef(Op2.getReg());
849 return MI1 && MI2 && (MI1->getParent() == MBB || MI2->getParent() == MBB);
862 MachineInstr *MI2 = MRI.getUniqueVRegDef(Inst.getOperand(2).getReg()); local
868 areOpcodesEqualOrInverse(Opcode, MI2->getOpcode());
870 std::swap(MI1, MI2);
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| /freebsd-current/contrib/llvm-project/llvm/lib/Target/AMDGPU/ |
| H A D | SIFixSGPRCopies.cpp | 475 MachineInstr *MI2 = *I2;
510 if (MDT.dominates(MI1, MI2)) {
511 if (!interferes(MI2, MI1)) {
514 << printMBBReference(*MI2->getParent()) << " " << *MI2);
515 MergedInstrs.insert(MI2);
520 } else if (MDT.dominates(MI2, MI1)) {
521 if (!interferes(MI1, MI2)) {
532 MI2->getParent());
539 if (!interferes(MI1, I) && !interferes(MI2,
[all...] |
| H A D | SIInstrInfo.cpp | 521 const MachineInstr &MI2,
529 if (!MI1.hasOneMemOperand() || !MI2.hasOneMemOperand())
533 auto MO2 = *MI2.memoperands_begin();
|
| /freebsd-current/contrib/llvm-project/llvm/include/llvm/CodeGen/GlobalISel/ |
| H A D | LoadStoreOpt.h | 61 /// \p MI2 \returns true if either alias/no-alias is known. Sets \p IsAlias
63 bool aliasIsKnownForLoadStore(const MachineInstr &MI1, const MachineInstr &MI2,
|
| /freebsd-current/contrib/llvm-project/llvm/lib/Target/Hexagon/ |
| H A D | HexagonVLIWPacketizer.h | 144 bool arePredicatesComplements(MachineInstr &MI1, MachineInstr &MI2);
|
| H A D | HexagonInstrInfo.h | 408 const MachineInstr &MI2) const;
420 const MachineInstr &MI2) const;
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| H A D | HexagonSubtarget.cpp | 277 MachineInstr &MI2 = *SI.getSUnit()->getInstr(); local
278 if (!QII->isHVXVec(MI2))
280 if ((IsStoreMI1 && MI2.mayStore()) || (IsLoadMI1 && MI2.mayLoad())) {
|
| H A D | HexagonVLIWPacketizer.cpp | 967 MachineInstr &MI2) {
971 getPredicateSense(MI2, HII) == PK_Unknown)
1024 unsigned PReg2 = getPredicatedRegister(MI2, HII);
1028 getPredicateSense(MI1, HII) != getPredicateSense(MI2, HII) &&
1029 HII->isDotNewInst(MI1) == HII->isDotNewInst(MI2);
966 arePredicatesComplements(MachineInstr &MI1, MachineInstr &MI2) argument
|
| H A D | HexagonInstrInfo.cpp | 2687 const MachineInstr &MI2) const {
2691 int N = MI2.getNumOperands();
2693 if (MI2.getOperand(I).isReg() && DstReg == MI2.getOperand(I).getReg())
2696 if (mayBeNewStore(MI2))
2697 if (MI2.getOpcode() == Hexagon::V6_vS32b_pi)
2698 if (MI1.getOperand(0).isReg() && MI2.getOperand(3).isReg() &&
2699 MI1.getOperand(0).getReg() == MI2.getOperand(3).getReg())
3035 const MachineInstr &MI2) const {
3036 if (isHVXVec(MI1) && isHVXVec(MI2))
[all...] |
| /freebsd-current/contrib/llvm-project/llvm/include/llvm/CodeGen/ |
| H A D | DFAPacketizer.h | 215 bool alias(const MachineInstr &MI1, const MachineInstr &MI2,
|
| /freebsd-current/contrib/llvm-project/llvm/lib/Target/X86/ |
| H A D | X86OptimizeLEAs.cpp | 274 /// and \p MI2. The numbers of the first memory operands for the instructions
277 const MachineInstr &MI2, unsigned N2) const;
395 // instructions \p MI1 and \p MI2. The numbers of the first memory operands are
399 const MachineInstr &MI2,
402 const MachineOperand &Op2 = MI2.getOperand(N2 + X86::AddrDisp);
397 getAddrDispShift(const MachineInstr &MI1, unsigned N1, const MachineInstr &MI2, unsigned N2) const argument
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| H A D | X86ISelLowering.h | 1757 MachineInstr &MI2,
|
| /freebsd-current/contrib/llvm-project/llvm/lib/Target/ARM/ |
| H A D | MLxExpansionPass.cpp | 314 MachineInstr &MI2 = *MII;
318 dbgs() << " " << MI2;
|
| /freebsd-current/contrib/llvm-project/llvm/lib/Target/RISCV/ |
| H A D | RISCVInstrInfo.h | 293 bool hasEqualFRM(const MachineInstr &MI1, const MachineInstr &MI2);
|
| H A D | RISCVInstrInfo.cpp | 2245 const MachineInstr &MI2,
2253 if (!MI1.hasOneMemOperand() || !MI2.hasOneMemOperand())
2257 auto MO2 = *MI2.memoperands_begin();
3278 bool RISCV::hasEqualFRM(const MachineInstr &MI1, const MachineInstr &MI2) { argument
3282 RISCV::getNamedOperandIdx(MI2.getOpcode(), RISCV::OpName::frm);
3286 MachineOperand FrmOp2 = MI2.getOperand(MI2FrmOpIdx);
2243 memOpsHaveSameBasePtr(const MachineInstr &MI1, ArrayRef<const MachineOperand *> BaseOps1, const MachineInstr &MI2, ArrayRef<const MachineOperand *> BaseOps2) argument
|
| /freebsd-current/contrib/llvm-project/llvm/lib/CodeGen/GlobalISel/ |
| H A D | LoadStoreOpt.cpp | 105 const MachineInstr &MI2,
109 auto *LdSt2 = dyn_cast<GLoadStore>(&MI2);
104 aliasIsKnownForLoadStore(const MachineInstr &MI1, const MachineInstr &MI2, bool &IsAlias, MachineRegisterInfo &MRI) argument
|
| /freebsd-current/contrib/llvm-project/llvm/lib/Target/AVR/ |
| H A D | AVRExpandPseudoInsts.cpp | 1655 auto MI2 = local
1661 MI2->getOperand(3).setIsDead();
1853 auto MI2 = local
1859 MI2->getOperand(3).setIsDead();
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| /freebsd-current/contrib/llvm-project/llvm/lib/CodeGen/AsmPrinter/ |
| H A D | AsmPrinter.cpp | 1758 auto MI2 = std::next(MI.getIterator()); local
1759 if (IsEHa && MI2 != MBB.end() &&
1760 (MI2->mayLoadOrStore() || MI2->mayRaiseFPException()))
|