/freebsd-current/contrib/llvm-project/llvm/lib/CodeGen/ |
H A D | RegisterCoalescer.h | 33 Register DstReg; member in class:llvm::CoalescerPair 38 /// The sub-register index of the old DstReg in the new coalesced register. 50 /// True when DstReg and SrcReg are reversed from the original 54 /// The register class of the coalesced register, or NULL if DstReg 56 /// SrcReg and DstReg. 66 : TRI(tri), DstReg(PhysReg), SrcReg(VirtReg) {} 72 /// Swap SrcReg and DstReg. Return false if swapping is impossible 73 /// because DstReg is a physical register, or SubIdx is set. 80 /// Return true if DstReg is a physical register. 87 /// Return true if DstReg i [all...] |
H A D | ExpandPostRAPseudos.cpp | 66 Register DstReg = MI->getOperand(0).getReg(); local 72 Register DstSubReg = TRI->getSubReg(DstReg, SubIdx); 74 assert(DstReg.isPhysical() && 94 if (DstReg != InsReg) { 106 // Implicitly define DstReg for subsequent uses. 109 CopyMI->addRegisterDefined(DstReg);
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H A D | OptimizePHIs.cpp | 100 Register DstReg = MI->getOperand(0).getReg(); local 113 if (SrcReg == DstReg) 144 Register DstReg = MI->getOperand(0).getReg(); local 145 assert(DstReg.isVirtual() && "PHI destination is not a virtual register"); 155 for (MachineInstr &UseMI : MRI->use_nodbg_instructions(DstReg)) {
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H A D | TwoAddressInstructionPass.cpp | 125 bool isCopyToReg(MachineInstr &MI, Register &SrcReg, Register &DstReg, 135 bool &IsCopy, Register &DstReg, 176 void scanUses(Register DstReg); 290 Register &DstReg, bool &IsSrcPhys, 293 DstReg = 0; 295 DstReg = MI.getOperand(0).getReg(); 298 DstReg = MI.getOperand(0).getReg(); 305 IsDstPhys = DstReg.isPhysical(); 387 Register SrcReg, DstReg; 390 if (!isCopyToReg(*DefMI, SrcReg, DstReg, IsSrcPhy 289 isCopyToReg(MachineInstr &MI, Register &SrcReg, Register &DstReg, bool &IsSrcPhys, bool &IsDstPhys) const argument [all...] |
/freebsd-current/contrib/llvm-project/llvm/lib/Target/Hexagon/ |
H A D | HexagonPeephole.cpp | 135 Register DstReg = Dst.getReg(); local 138 if (DstReg.isVirtual() && SrcReg.isVirtual()) { 142 PeepholeMap[DstReg] = SrcReg; 155 Register DstReg = Dst.getReg(); local 157 PeepholeMap[DstReg] = SrcReg; 172 Register DstReg = Dst.getReg(); local 174 PeepholeDoubleRegsMap[DstReg] = 183 Register DstReg = Dst.getReg(); local 186 if (DstReg.isVirtual() && SrcReg.isVirtual()) { 190 PeepholeMap[DstReg] 205 Register DstReg = Dst.getReg(); local [all...] |
/freebsd-current/contrib/llvm-project/llvm/include/llvm/CodeGen/GlobalISel/ |
H A D | LegalizationArtifactCombiner.h | 66 Register DstReg = MI.getOperand(0).getReg(); local 73 if (MRI.getType(DstReg) == MRI.getType(TruncSrc)) 74 replaceRegOrBuildCopy(DstReg, TruncSrc, MRI, Builder, UpdatedDefs, 77 Builder.buildAnyExtOrTrunc(DstReg, TruncSrc); 78 UpdatedDefs.push_back(DstReg); 90 Builder.buildInstr(ExtMI->getOpcode(), {DstReg}, {ExtSrc}); 91 UpdatedDefs.push_back(DstReg); 99 const LLT DstTy = MRI.getType(DstReg); 103 DstReg, CstVal.getCImm()->getValue().sext(DstTy.getSizeInBits())); 104 UpdatedDefs.push_back(DstReg); 120 Register DstReg = MI.getOperand(0).getReg(); local 194 Register DstReg = MI.getOperand(0).getReg(); local 252 Register DstReg = MI.getOperand(0).getReg(); local 373 Register DstReg = MI.getOperand(0).getReg(); local 547 replaceRegOrBuildCopy(Register DstReg, Register SrcReg, MachineRegisterInfo &MRI, MachineIRBuilder &Builder, SmallVectorImpl<Register> &UpdatedDefs, GISelChangeObserver &Observer) argument 1223 Register DstReg = MI.getOperand(Idx).getReg(); local [all...] |
/freebsd-current/contrib/llvm-project/llvm/lib/Target/AVR/ |
H A D | AVRExpandPseudoInsts.cpp | 61 Register DstReg) { 62 return BuildMI(MBB, MBBI, MBBI->getDebugLoc(), TII->get(Opcode), DstReg); 154 Register DstReg = MI.getOperand(0).getReg(); 161 TRI->splitReg(DstReg, DstLoReg, DstHiReg); 187 Register DstReg = MI.getOperand(0).getReg(); local 194 TRI->splitReg(DstReg, DstLoReg, DstHiReg); 247 Register DstReg = MI.getOperand(0).getReg(); local 254 TRI->splitReg(DstReg, DstLoReg, DstHiReg); 307 Register DstReg = MI.getOperand(0).getReg(); local 311 TRI->splitReg(DstReg, DstLoRe 60 buildMI(Block &MBB, BlockIt MBBI, unsigned Opcode, Register DstReg) argument 361 Register DstReg = MI.getOperand(0).getReg(); local 426 Register DstReg = MI.getOperand(0).getReg(); local 458 Register DstReg = MI.getOperand(0).getReg(); local 497 Register DstReg = MI.getOperand(0).getReg(); local 530 Register DstReg = MI.getOperand(0).getReg(); local 565 Register DstReg = MI.getOperand(0).getReg(); local 616 Register DstReg = MI.getOperand(0).getReg(); local 661 Register DstReg = MI.getOperand(0).getReg(); local 706 Register DstReg = MI.getOperand(0).getReg(); local 739 Register DstReg = MI.getOperand(0).getReg(); local 771 Register DstReg = MI.getOperand(0).getReg(); local 839 Register DstReg = MI.getOperand(0).getReg(); local 951 Register DstReg = MI.getOperand(0).getReg(); local 1149 Register DstReg = MI.getOperand(0).getReg(); local 1202 Register DstReg = MI.getOperand(0).getReg(); local 1237 Register DstReg = MI.getOperand(0).getReg(); local 1273 Register DstReg = MI.getOperand(0).getReg(); local 1383 Register DstReg = MI.getOperand(0).getReg(); local 1471 Register DstReg = MI.getOperand(0).getReg(); local 1493 Register DstReg = MI.getOperand(0).getReg(); local 1541 Register DstReg = MI.getOperand(0).getReg(); local 1564 Register DstReg = MI.getOperand(0).getReg(); local 1598 Register DstReg = MI.getOperand(0).getReg(); local 1621 Register DstReg = MI.getOperand(0).getReg(); local 1679 Register DstReg = MI.getOperand(0).getReg(); local 1706 Register DstReg = MI.getOperand(0).getReg(); local 1765 Register DstReg = MI.getOperand(0).getReg(); local 1797 Register DstReg = MI.getOperand(0).getReg(); local 1819 Register DstReg = MI.getOperand(0).getReg(); local 1877 Register DstReg = MI.getOperand(0).getReg(); local 1904 Register DstReg = MI.getOperand(0).getReg(); local 1975 Register DstReg = MI.getOperand(0).getReg(); local 2007 Register DstReg = MI.getOperand(0).getReg(); local 2029 Register DstReg = MI.getOperand(0).getReg(); local 2076 Register DstReg = MI.getOperand(0).getReg(); local 2111 Register DstReg = MI.getOperand(0).getReg(); local 2165 Register DstReg = MI.getOperand(0).getReg(); local 2221 Register DstReg = MI.getOperand(0).getReg(); local 2271 Register DstReg = MI.getOperand(0).getReg(); local 2323 Register DstReg = MI.getOperand(0).getReg(); local 2361 Register DstReg = MI.getOperand(0).getReg(); local 2421 Register DstReg = MI.getOperand(0).getReg(); local 2473 Register DstReg = MI.getOperand(0).getReg(); local 2503 Register DstReg = MI.getOperand(0).getReg(); local [all...] |
H A D | AVRRegisterInfo.cpp | 113 Register DstReg) { 122 // Check that DstReg matches with next instruction, otherwise the instruction 124 if (DstReg != MI.getOperand(0).getReg()) { 169 Register DstReg = MI.getOperand(0).getReg(); local 170 assert(DstReg != AVR::R29R28 && "Dest reg cannot be the frame pointer"); 174 BuildMI(MBB, MI, dl, TII.get(AVR::MOVWRdRr), DstReg) 178 splitReg(DstReg, DstLoReg, DstHiReg); 201 foldFrameOffset(II, Offset, DstReg); 203 // Select the best opcode based on DstReg and the offset size. 204 switch (DstReg) { 112 foldFrameOffset(MachineBasicBlock::iterator &II, int &Offset, Register DstReg) argument [all...] |
/freebsd-current/contrib/llvm-project/llvm/lib/Target/AMDGPU/ |
H A D | R600ExpandSpecialInstrs.cpp | 126 Register DstReg = MI.getOperand(0).getReg(); local 127 unsigned DstBase = TRI.getEncodingValue(DstReg) & HW_REG_MASK; 130 bool Mask = (Chan != TRI.getHWRegChan(DstReg)); 196 Register DstReg = local 226 DstReg = TRI.getSubReg(DstReg, SubRegIndex); 230 Mask = (Chan != TRI.getHWRegChan(DstReg)); 231 unsigned DstBase = TRI.getEncodingValue(DstReg) & HW_REG_MASK; 232 DstReg = R600::R600_TReg32RegClass.getRegister((DstBase * 4) + Chan); 252 TII->buildDefaultInstruction(MBB, I, Opcode, DstReg, Src [all...] |
H A D | SILowerI1Copies.cpp | 69 void markAsLaneMask(Register DstReg) const override; 79 Register DstReg, Register PrevReg, 474 Register DstReg = MI.getOperand(0).getReg(); 479 if (isLaneMaskReg(DstReg) || isVreg1(DstReg)) 488 assert(isVRegCompatibleReg(TII->getRegisterInfo(), *MRI, DstReg)); 492 BuildMI(MBB, MI, DL, TII->get(AMDGPU::V_CNDMASK_B32_e64), DstReg) 559 Register DstReg = MI->getOperand(0).getReg(); 560 markAsLaneMask(DstReg); 561 initializeLaneMaskRegisterAttributes(DstReg); [all...] |
H A D | SILowerI1Copies.h | 82 virtual void markAsLaneMask(Register DstReg) const = 0; 92 const DebugLoc &DL, Register DstReg,
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/freebsd-current/contrib/llvm-project/llvm/lib/Target/LoongArch/ |
H A D | LoongArchInstrInfo.cpp | 41 const DebugLoc &DL, MCRegister DstReg, 43 if (LoongArch::GPRRegClass.contains(DstReg, SrcReg)) { 44 BuildMI(MBB, MBBI, DL, get(LoongArch::OR), DstReg) 51 if (LoongArch::LSX128RegClass.contains(DstReg, SrcReg)) { 52 BuildMI(MBB, MBBI, DL, get(LoongArch::VORI_B), DstReg) 59 if (LoongArch::LASX256RegClass.contains(DstReg, SrcReg)) { 60 BuildMI(MBB, MBBI, DL, get(LoongArch::XVORI_B), DstReg) 67 if (LoongArch::CFRRegClass.contains(DstReg) && 69 BuildMI(MBB, MBBI, DL, get(LoongArch::MOVGR2CF), DstReg) 74 if (LoongArch::GPRRegClass.contains(DstReg) 39 copyPhysReg(MachineBasicBlock &MBB, MachineBasicBlock::iterator MBBI, const DebugLoc &DL, MCRegister DstReg, MCRegister SrcReg, bool KillSrc) const argument 146 loadRegFromStackSlot(MachineBasicBlock &MBB, MachineBasicBlock::iterator I, Register DstReg, int FI, const TargetRegisterClass *RC, const TargetRegisterInfo *TRI, Register VReg) const argument 183 movImm(MachineBasicBlock &MBB, MachineBasicBlock::iterator MBBI, const DebugLoc &DL, Register DstReg, uint64_t Val, MachineInstr::MIFlag Flag) const argument [all...] |
H A D | LoongArchInstrInfo.h | 33 const DebugLoc &DL, MCRegister DstReg, MCRegister SrcReg, 43 MachineBasicBlock::iterator MBBI, Register DstReg, 48 // Materializes the given integer Val into DstReg. 50 const DebugLoc &DL, Register DstReg, uint64_t Val,
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/freebsd-current/contrib/llvm-project/llvm/lib/Target/CSKY/ |
H A D | CSKYInstrInfo.cpp | 233 Register DstReg; local 235 DstReg = MRI.createVirtualRegister(&CSKY::GPRRegClass); 238 BuildMI(MBB, MBBI, DL, get(CSKY::MOVI32), DstReg) 242 BuildMI(MBB, MBBI, DL, get(CSKY::MOVIH32), DstReg) 246 BuildMI(MBB, MBBI, DL, get(CSKY::MOVIH32), DstReg) 249 BuildMI(MBB, MBBI, DL, get(CSKY::ORI32), DstReg) 250 .addReg(DstReg) 256 DstReg = MRI.createVirtualRegister(&CSKY::mGPRRegClass); 258 BuildMI(MBB, MBBI, DL, get(CSKY::MOVI16), DstReg) 262 BuildMI(MBB, MBBI, DL, get(CSKY::MOVI16), DstReg) [all...] |
/freebsd-current/contrib/llvm-project/llvm/lib/Target/BPF/ |
H A D | BPFMISimplifyPatchable.cpp | 65 MachineInstr &MI, Register &SrcReg, Register &DstReg, 67 void processDstReg(MachineRegisterInfo *MRI, Register &DstReg, 191 Register &DstReg, const GlobalValue *GVal, bool IsAma) { 192 if (MRI->getRegClass(DstReg) == &BPF::GPR32RegClass) { 200 auto Begin = MRI->use_begin(DstReg), End = MRI->use_end(); 210 processDstReg(MRI, TmpReg, DstReg, GVal, false, IsAma); 215 BuildMI(MBB, MI, MI.getDebugLoc(), TII->get(BPF::COPY), DstReg) 220 // All uses of DstReg replaced by SrcReg 221 processDstReg(MRI, DstReg, SrcReg, GVal, true, IsAma); 225 Register &DstReg, Registe 189 processCandidate(MachineRegisterInfo *MRI, MachineBasicBlock &MBB, MachineInstr &MI, Register &SrcReg, Register &DstReg, const GlobalValue *GVal, bool IsAma) argument 224 processDstReg(MachineRegisterInfo *MRI, Register &DstReg, Register &SrcReg, const GlobalValue *GVal, bool doSrcRegProp, bool IsAma) argument 329 Register DstReg = MI.getOperand(0).getReg(); local [all...] |
/freebsd-current/contrib/llvm-project/llvm/lib/Target/SystemZ/ |
H A D | SystemZCopyPhysRegs.cpp | 79 Register DstReg = MI->getOperand(0).getReg(); local 80 if (DstReg.isVirtual() && 91 SystemZ::AR32BitRegClass.contains(DstReg)) { 94 BuildMI(MBB, MBBI, DL, TII->get(SystemZ::SAR), DstReg).addReg(Tmp);
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/freebsd-current/contrib/llvm-project/llvm/lib/Target/Hexagon/MCTargetDesc/ |
H A D | HexagonMCDuplexInfo.cpp | 190 unsigned DstReg, PredReg, SrcReg, Src1Reg, Src2Reg; local 201 DstReg = MCI.getOperand(0).getReg(); 205 if (HexagonMCInstrInfo::isIntRegForSubInst(DstReg)) { 219 DstReg = MCI.getOperand(0).getReg(); 221 if (HexagonMCInstrInfo::isIntRegForSubInst(DstReg) && 240 DstReg = MCI.getOperand(0).getReg(); 242 if (HexagonMCInstrInfo::isIntRegForSubInst(DstReg) && 250 DstReg = MCI.getOperand(0).getReg(); 252 if (HexagonMCInstrInfo::isIntRegForSubInst(DstReg) && 260 DstReg 536 unsigned DstReg, SrcReg; local [all...] |
H A D | HexagonMCCompound.cpp | 81 unsigned DstReg, SrcReg, Src1Reg, Src2Reg; local 97 DstReg = MI.getOperand(0).getReg(); 100 if ((Hexagon::P0 == DstReg || Hexagon::P1 == DstReg) && 111 DstReg = MI.getOperand(0).getReg(); 113 if ((Hexagon::P0 == DstReg || Hexagon::P1 == DstReg) && 123 DstReg = MI.getOperand(0).getReg(); 125 if (HexagonMCInstrInfo::isIntRegForSubInst(DstReg) && 133 DstReg [all...] |
/freebsd-current/contrib/llvm-project/llvm/lib/CodeGen/GlobalISel/ |
H A D | InstructionSelect.cpp | 178 auto [DstReg, SrcReg] = MI.getFirst2Regs(); 184 const TargetRegisterClass *DstRC = MRI.getRegClassOrNull(DstReg); 187 assert(canReplaceReg(DstReg, SrcReg, MRI) && 190 MRI.replaceRegWith(DstReg, SrcReg); 244 Register DstReg = MI.getOperand(0).getReg(); local 245 if (SrcReg.isVirtual() && DstReg.isVirtual()) { 247 auto DstRC = MRI.getRegClass(DstReg); 249 MRI.replaceRegWith(DstReg, SrcReg);
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/freebsd-current/contrib/llvm-project/llvm/lib/Target/X86/GISel/ |
H A D | X86InstructionSelector.cpp | 111 const unsigned DstReg, 126 bool emitInsertSubreg(unsigned DstReg, unsigned SrcReg, MachineInstr &I, 129 bool emitExtractSubreg(unsigned DstReg, unsigned SrcReg, MachineInstr &I, 272 Register DstReg = I.getOperand(0).getReg(); local 273 const unsigned DstSize = RBI.getSizeInBits(DstReg, MRI, TRI); 274 const RegisterBank &DstRegBank = *RBI.getRegBank(DstReg, MRI, TRI); 280 if (DstReg.isPhysical()) { 288 const TargetRegisterClass *DstRC = getRegClassFromGRPhysReg(DstReg); 317 getRegClass(MRI.getType(DstReg), DstRegBank); 335 const TargetRegisterClass *OldRC = MRI.getRegClassOrNull(DstReg); 740 selectTurnIntoCOPY( MachineInstr &I, MachineRegisterInfo &MRI, const unsigned DstReg, const TargetRegisterClass *DstRC, const unsigned SrcReg, const TargetRegisterClass *SrcRC) const argument 762 const Register DstReg = I.getOperand(0).getReg(); local 826 const Register DstReg = I.getOperand(0).getReg(); local 891 const Register DstReg = I.getOperand(0).getReg(); local 1092 const Register DstReg = I.getOperand(0).getReg(); local 1195 const Register DstReg = I.getOperand(0).getReg(); local 1246 emitExtractSubreg(unsigned DstReg, unsigned SrcReg, MachineInstr &I, MachineRegisterInfo &MRI, MachineFunction &MF) const argument 1284 emitInsertSubreg(unsigned DstReg, unsigned SrcReg, MachineInstr &I, MachineRegisterInfo &MRI, MachineFunction &MF) const argument 1327 const Register DstReg = I.getOperand(0).getReg(); local 1412 Register DstReg = I.getOperand(0).getReg(); local 1486 const Register DstReg = I.getOperand(0).getReg(); local 1548 Register DstReg = I.getOperand(0).getReg(); local 1582 const Register DstReg = I.getOperand(0).getReg(); local 1801 unsigned DstReg = Sel.getReg(0); local [all...] |
/freebsd-current/contrib/llvm-project/llvm/lib/Target/X86/ |
H A D | X86LowerTileCopy.cpp | 84 Register DstReg = DstMO.getReg(); local 85 if (!X86::TILERegClass.contains(DstReg, SrcReg)) 121 NewMI = addFrameReference(BuildMI(MBB, MI, DL, TII->get(Opc), DstReg),
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/freebsd-current/contrib/llvm-project/llvm/lib/Target/AArch64/ |
H A D | AArch64RedundantCopyElimination.cpp | 185 MCPhysReg DstReg = PredI.getOperand(0).getReg(); 194 SrcReg != DstReg) { 208 if (DstReg == AArch64::WZR || DstReg == AArch64::XZR) 213 if (!DomBBClobberedRegs.available(DstReg)) 217 KnownRegs.push_back(RegImm(DstReg, 0)); 251 MCPhysReg DstReg = PredI.getOperand(0).getReg(); local 252 if (DstReg == AArch64::WZR || DstReg == AArch64::XZR) 257 if (!DomBBClobberedRegs.available(DstReg)) [all...] |
/freebsd-current/contrib/llvm-project/llvm/lib/Target/RISCV/ |
H A D | RISCVPostRAExpandPseudoInsts.cpp | 95 Register DstReg = MBBI->getOperand(0).getReg(); local 99 TII->movImm(MBB, MBBI, DL, DstReg, Val, MachineInstr::NoFlags, Renamable,
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/freebsd-current/contrib/llvm-project/llvm/lib/Target/PowerPC/GISel/ |
H A D | PPCInstructionSelector.cpp | 133 Register DstReg = I.getOperand(0).getReg(); local 135 if (DstReg.isPhysical()) 138 const RegisterBank *DstRegBank = RBI.getRegBank(DstReg, MRI, TRI); 140 getRegClass(MRI.getType(DstReg), DstRegBank); 145 if (!RBI.constrainGenericRegister(DstReg, *DstRC, MRI)) { 191 const Register DstReg = I.getOperand(0).getReg(); local 199 bool IsSingle = MRI.getType(DstReg).getSizeInBits() == 32; 205 BuildMI(MBB, I, DbgLoc, TII.get(ConvOp), DstReg).addReg(MoveReg); 218 const Register DstReg = I.getOperand(0).getReg(); local 235 BuildMI(MBB, I, DbgLoc, TII.get(PPC::MFVSRD), DstReg) 243 const Register DstReg = I.getOperand(0).getReg(); local [all...] |
/freebsd-current/contrib/llvm-project/llvm/lib/Target/RISCV/GISel/ |
H A D | RISCVInstructionSelector.cpp | 266 Register DstReg = MRI.createVirtualRegister(&RISCV::GPRRegClass); 269 .buildInstr(RISCV::SRLI, {DstReg}, {RegY}) 271 MIB.addReg(DstReg); 278 Register DstReg = MRI.createVirtualRegister(&RISCV::GPRRegClass); 281 .buildInstr(RISCV::SRLI, {DstReg}, {RegY}) 283 MIB.addReg(DstReg); 317 Register DstReg = MRI.createVirtualRegister(&RISCV::GPRRegClass); 320 .buildInstr(RISCV::SRLIW, {DstReg}, {RegY}) 322 MIB.addReg(DstReg); 356 Register DstReg [all...] |