X86/GISel/X86InstructionSelector.cpp

111                           const unsigned DstReg,
126   bool emitInsertSubreg(unsigned DstReg, unsigned SrcReg, MachineInstr &I,
129   bool emitExtractSubreg(unsigned DstReg, unsigned SrcReg, MachineInstr &I,
272   Register DstReg = I.getOperand(0).getReg();
273   const unsigned DstSize = RBI.getSizeInBits(DstReg, MRI, TRI);
274   const RegisterBank &DstRegBank = *RBI.getRegBank(DstReg, MRI, TRI);
280   if (DstReg.isPhysical()) {
288       const TargetRegisterClass *DstRC = getRegClassFromGRPhysReg(DstReg);
317       getRegClass(MRI.getType(DstReg), DstRegBank);
335   const TargetRegisterClass *OldRC = MRI.getRegClassOrNull(DstReg);
337     if (!RBI.constrainGenericRegister(DstReg, *DstRC, MRI)) {
741     MachineInstr &I, MachineRegisterInfo &MRI, const unsigned DstReg,
746       !RBI.constrainGenericRegister(DstReg, *DstRC, MRI)) {
762   const Register DstReg = I.getOperand(0).getReg();
765   const LLT DstTy = MRI.getType(DstReg);
768   const RegisterBank &DstRB = *RBI.getRegBank(DstReg, MRI, TRI);
787     return selectTurnIntoCOPY(I, MRI, DstReg, DstRC, SrcReg, SrcRC);
809       !RBI.constrainGenericRegister(DstReg, *DstRC, MRI)) {
826   const Register DstReg = I.getOperand(0).getReg();
829   const LLT DstTy = MRI.getType(DstReg);
863         MRI.createVirtualRegister(getRegClass(DstTy, DstReg, MRI));
867     DefReg = MRI.createVirtualRegister(getRegClass(DstTy, DstReg, MRI));
876       *BuildMI(*I.getParent(), I, I.getDebugLoc(), TII.get(AndOpc), DstReg)
891   const Register DstReg = I.getOperand(0).getReg();
894   const LLT DstTy = MRI.getType(DstReg);
897   const RegisterBank &DstRB = *RBI.getRegBank(DstReg, MRI, TRI);
913     return selectTurnIntoCOPY(I, MRI, SrcReg, SrcRC, DstReg, DstRC);
919       !RBI.constrainGenericRegister(DstReg, *DstRC, MRI)) {
932       .addDef(DstReg)
1092   const Register DstReg = I.getOperand(0).getReg();
1101   const LLT DstTy = MRI.getType(DstReg);
1135   const RegisterBank &DstRB = *RBI.getRegBank(DstReg, MRI, TRI);
1174       *BuildMI(*I.getParent(), I, I.getDebugLoc(), TII.get(Opcode), DstReg)
1195   const Register DstReg = I.getOperand(0).getReg();
1199   const LLT DstTy = MRI.getType(DstReg);
1211     if (!emitExtractSubreg(DstReg, SrcReg, I, MRI, MF))
1246 bool X86InstructionSelector::emitExtractSubreg(unsigned DstReg, unsigned SrcReg,
1250   const LLT DstTy = MRI.getType(DstReg);
1267   const TargetRegisterClass *DstRC = getRegClass(DstTy, DstReg, MRI);
1273       !RBI.constrainGenericRegister(DstReg, *DstRC, MRI)) {
1278   BuildMI(*I.getParent(), I, I.getDebugLoc(), TII.get(X86::COPY), DstReg)
1284 bool X86InstructionSelector::emitInsertSubreg(unsigned DstReg, unsigned SrcReg,
1288   const LLT DstTy = MRI.getType(DstReg);
1307   const TargetRegisterClass *DstRC = getRegClass(DstTy, DstReg, MRI);
1310       !RBI.constrainGenericRegister(DstReg, *DstRC, MRI)) {
1316       .addReg(DstReg, RegState::DefineNoRead, SubIdx)
1327   const Register DstReg = I.getOperand(0).getReg();
1332   const LLT DstTy = MRI.getType(DstReg);
1344     if (!emitInsertSubreg(DstReg, InsertReg, I, MRI, MF))
1412   Register DstReg = I.getOperand(0).getReg();
1415   const LLT DstTy = MRI.getType(DstReg);
1419   const RegisterBank &RegBank = *RBI.getRegBank(DstReg, MRI, TRI);
1444                                     TII.get(TargetOpcode::COPY), DstReg)
1486   const Register DstReg = I.getOperand(0).getReg();
1487   const LLT DstTy = MRI.getType(DstReg);
1488   const RegisterBank &RegBank = *RBI.getRegBank(DstReg, MRI, TRI);
1514         addDirectMem(BuildMI(*I.getParent(), I, DbgLoc, TII.get(Opc), DstReg),
1532         BuildMI(*I.getParent(), I, DbgLoc, TII.get(Opc), DstReg), CPI, PICBase,
1548   Register DstReg = I.getOperand(0).getReg();
1550   if (!MRI.getRegClassOrNull(DstReg)) {
1551     const LLT DstTy = MRI.getType(DstReg);
1552     const TargetRegisterClass *RC = getRegClass(DstTy, DstReg, MRI);
1554     if (!RBI.constrainGenericRegister(DstReg, *RC, MRI)) {
1582   const Register DstReg = I.getOperand(0).getReg();
1586   const LLT RegTy = MRI.getType(DstReg);
1590   const RegisterBank *RegRB = RBI.getRegBank(DstReg, MRI, TRI);
1714       !RBI.constrainGenericRegister(DstReg, *RegRC, MRI)) {
1783         .addDef(DstReg)
1789             DstReg)
1801   unsigned DstReg = Sel.getReg(0);
1807   LLT Ty = MRI.getType(DstReg);
1825   BuildMI(*Sel.getParent(), Sel, Sel.getDebugLoc(), TII.get(OpCmp), DstReg)
1830   const TargetRegisterClass *DstRC = getRegClass(Ty, DstReg, MRI);
1831   if (!RBI.constrainGenericRegister(DstReg, *DstRC, MRI)) {