Searched refs:mclk (Results 1 - 11 of 11) sorted by relevance
/freebsd-9.3-release/sys/dev/drm2/radeon/ |
H A D | radeon_pm.c | 164 u32 sclk, mclk; local 179 * mclk. 186 mclk = rdev->pm.power_state[rdev->pm.requested_power_state_index]. 187 clock_info[rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_on_cm_idx].mclk; 189 mclk = rdev->pm.power_state[rdev->pm.requested_power_state_index]. 190 clock_info[rdev->pm.requested_clock_mode_index].mclk; 192 if (mclk > rdev->pm.default_mclk) 193 mclk = rdev->pm.default_mclk; 222 if (rdev->asic->pm.set_memory_clock && (mclk != rdev->pm.current_mclk)) { 224 radeon_set_memory_clock(rdev, mclk); [all...] |
H A D | radeon_atombios.c | 2030 rdev->pm.power_state[state_index].clock_info[0].mclk = 2035 if ((rdev->pm.power_state[state_index].clock_info[0].mclk == 0) || 2065 rdev->pm.power_state[state_index].clock_info[0].mclk = 2070 if ((rdev->pm.power_state[state_index].clock_info[0].mclk == 0) || 2101 rdev->pm.power_state[state_index].clock_info[0].mclk = 2106 if ((rdev->pm.power_state[state_index].clock_info[0].mclk == 0) || 2301 rdev->pm.default_mclk = rdev->pm.power_state[state_index].clock_info[0].mclk; 2305 /* patch the table values with the default slck/mclk from firmware info */ 2307 rdev->pm.power_state[state_index].clock_info[j].mclk = 2323 u32 sclk, mclk; local [all...] |
H A D | radeon_clocks.c | 73 uint32_t fb_div, ref_div, post_div, mclk; local 86 mclk = fb_div / ref_div; 90 mclk >>= 1; 92 mclk >>= 2; 94 mclk >>= 3; 96 return mclk;
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H A D | radeon_device.c | 486 * Used when sclk/mclk are switched or display modes are set. 493 u32 mclk = rdev->pm.current_mclk; local 495 /* sclk/mclk in Mhz */ 499 rdev->pm.mclk.full = dfixed_const(mclk); 500 rdev->pm.mclk.full = dfixed_div(rdev->pm.mclk, a);
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H A D | radeon_combios.c | 802 uint16_t sclk, mclk; local 855 /* default sclk/mclk */ 857 mclk = RBIOS16(pll_info + 0x8); 860 if (mclk == 0) 861 mclk = 200 * 100; 864 rdev->clock.default_mclk = mclk; 2785 rdev->pm.power_state[state_index].clock_info[0].mclk = RBIOS32(offset + 0x5 + 0x2); 2787 if ((rdev->pm.power_state[state_index].clock_info[0].mclk == 0) || 2859 rdev->pm.power_state[state_index].clock_info[0].mclk = rdev->clock.default_mclk;
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H A D | radeon.h | 1036 u32 mclk; member in struct:radeon_pm_clock_info 1068 /* write locked while reprogramming mclk */ 1084 fixed20_12 mclk; member in struct:radeon_pm
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H A D | r100.c | 261 clock_info[rdev->pm.requested_clock_mode_index].mclk, 3316 mclk_ff = rdev->pm.mclk;
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H A D | r600.c | 286 clock_info[rdev->pm.requested_clock_mode_index].mclk,
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/freebsd-9.3-release/sys/dev/sound/macio/ |
H A D | i2s.c | 451 u_int mclk, mdiv, sdiv; local 467 mclk = rate * MCLK_FS; 471 if ((clksrc[i].cs_clock % mclk) == 0) { 473 mdiv = clksrc[i].cs_clock / mclk;
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/freebsd-9.3-release/sys/dev/cxgb/common/ |
H A D | cxgb_t3_hw.c | 628 VPD_ENTRY(mclk, 6); /* mem clock */ 883 p->mclk = simple_strtoul(vpd.mclk_data, NULL, 10); 4152 if (vpd->mclk) { 4155 if (mc7_init(&adapter->pmrx, vpd->mclk, vpd->mem_timing) || 4156 mc7_init(&adapter->pmtx, vpd->mclk, vpd->mem_timing) || 4157 mc7_init(&adapter->cm, vpd->mclk, vpd->mem_timing) || 4491 if (adapter->params.vpd.mclk) {
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H A D | cxgb_common.h | 351 unsigned int mclk; member in struct:vpd_params
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